A coarse grain reconfigurable processor architecture for stream processing engine

Takefumi Miyoshi, Hideyuki Kawashima, Yuta Terada, Tsutomu Yoshinaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

This paper proposes a processor architecture for DR-SPE, a dynamic reconfigurable stream processing engine. DR-SPE is special-purpose hardware for stream data processing, which achieves high processing performance by exploiting parallelism in the target query. It also handles query registration and execution order of operations at runtime. Available operations in DR-SPE are the same as those in Streams on Wires. In this paper, DR-SPE is implemented on a FPGA XC6VLX240T-1, and its performance is evaluated. The results of the evaluation show that DR-SPE achieves register modification within 506 μsec when the configuration path is driven at 1 Mbps, which is not achieved by Streams on Wires. DR-SPE also achieves flexibility and can support complicated queries by providing 10×10 operation units tiled onto an FPGA. DR-SPE achieves comparable operation throughput with Streams on Wires at the expense of requiring more LUTs.

Original languageEnglish
Title of host publicationProceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011
Pages490-495
Number of pages6
DOIs
Publication statusPublished - 2011 Nov 9
Externally publishedYes
Event21st International Conference on Field Programmable Logic and Applications, FPL 2011 - Chania, Greece
Duration: 2011 Sep 52011 Sep 7

Other

Other21st International Conference on Field Programmable Logic and Applications, FPL 2011
CountryGreece
CityChania
Period11/9/511/9/7

Fingerprint

Wire
Engines
Field programmable gate arrays (FPGA)
Processing
Throughput
Hardware

ASJC Scopus subject areas

  • Computer Science Applications

Cite this

Miyoshi, T., Kawashima, H., Terada, Y., & Yoshinaga, T. (2011). A coarse grain reconfigurable processor architecture for stream processing engine. In Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011 (pp. 490-495). [6044870] https://doi.org/10.1109/FPL.2011.97

A coarse grain reconfigurable processor architecture for stream processing engine. / Miyoshi, Takefumi; Kawashima, Hideyuki; Terada, Yuta; Yoshinaga, Tsutomu.

Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011. 2011. p. 490-495 6044870.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Miyoshi, T, Kawashima, H, Terada, Y & Yoshinaga, T 2011, A coarse grain reconfigurable processor architecture for stream processing engine. in Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011., 6044870, pp. 490-495, 21st International Conference on Field Programmable Logic and Applications, FPL 2011, Chania, Greece, 11/9/5. https://doi.org/10.1109/FPL.2011.97
Miyoshi T, Kawashima H, Terada Y, Yoshinaga T. A coarse grain reconfigurable processor architecture for stream processing engine. In Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011. 2011. p. 490-495. 6044870 https://doi.org/10.1109/FPL.2011.97
Miyoshi, Takefumi ; Kawashima, Hideyuki ; Terada, Yuta ; Yoshinaga, Tsutomu. / A coarse grain reconfigurable processor architecture for stream processing engine. Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011. 2011. pp. 490-495
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