A coarse-grained reconfigurable architecture with a fault tolerant non-volatile configurable memory

Takeharu Ikezoe, Takuya Kojima, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Recent IoT devices require extremely low standby power consumption, while a certain performance is needed during the active time, and Coarse Grain Reconfigurable Arrays (CGRAs) are suitable because of their high energy efficiency. However, even in CGRAs, the leakage power for its configuration memory must be reduced. Although the power gating is a popular technique, the data in flip-flops and memory are lost so they must be retrieved after the wake-up. Recovering everything requires numerous state transitions and considerable overhead both on its execution time and energy. To address the problem, Non-volatile Cool Mega Array (NVCMA), a CGRA providing non-volatile flip-flops (NVFFs) with spin transfer torque type non-volatile memory (NVM) technology has been developed. However, in general, non-volatile memory technologies have problems with reliability. Some NVFFs are stacked-at-0/1, and cannot store the data in a certain possibility. To improve the chip yield, we propose a mapping algorithm to avoid faulty processing elements of the CGRA caused by the erroneous configuration data. Then, we also propose a method to add an error-correcting code (ECC) mechanism to NVFFs used for the configuration and constant memory. The proposed method was applied to NVCMA to evaluate the availability rate and reduction of write time. By using both methods, the 99.4% availability ratio is achieved with 0.1% probability of faulty FFs, while almost no chips are available without using them. The energy for storing data becomes about 2.28 times because of the hardware overhead of ECC but the proposed method can save 11.1% of the storing energy on average.

Original languageEnglish
Title of host publicationProceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages81-89
Number of pages9
ISBN (Electronic)9781728129433
DOIs
Publication statusPublished - 2019 Dec
Event18th International Conference on Field-Programmable Technology, ICFPT 2019 - Tianjin, China
Duration: 2019 Dec 92019 Dec 13

Publication series

NameProceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019
Volume2019-December

Conference

Conference18th International Conference on Field-Programmable Technology, ICFPT 2019
CountryChina
CityTianjin
Period19/12/919/12/13

Keywords

  • Coarse Grained Reconfigurable Architecture
  • Fault Tolerance
  • Non volatile Flip flops

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Artificial Intelligence
  • Computational Theory and Mathematics
  • Hardware and Architecture

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  • Cite this

    Ikezoe, T., Kojima, T., & Amano, H. (2019). A coarse-grained reconfigurable architecture with a fault tolerant non-volatile configurable memory. In Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019 (pp. 81-89). [8977850] (Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019; Vol. 2019-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICFPT47387.2019.00018