A cost-effective context memory structure for dynamically reconfigurable processors

Masayasu Suzuki, Yohei Hasegawa, Vu Manh Tuan, Shohei Abe, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

Multicontext reconfigurable processors can switch its configuration in a single clock cycle by providing a context memory in each of the processing elements. Although these processors have proven to be powerful in many applications, the number of contexts is often not enough. The context translation table which translates the global instruction pointer, or the global logical context number, into a local physical context number is proposed to realize a larger application while reducing the actual context memories. Our evaluation using NEC Electronics' DRP-1 shows that the proposed method is effective when the size of the tile is small and the number of context is large. In the most efficient case, the required number of contexts is reduced to 25%, and the total amount of configuration data becomes 6.9%. The template configuration method which extends this idea harnesses the power of multicontext devices by storing basic contexts as templates and combining them to form the actual contexts. While effective in theory, our evaluation shows that the return in adopting such mechanisms in more finer processors as the DRP-1 is minimal where the size of the context memory adds up relative to the number of processing units.

Original languageEnglish
Title of host publication20th International Parallel and Distributed Processing Symposium, IPDPS 2006
Volume2006
DOIs
Publication statusPublished - 2006

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Data storage equipment
Costs
Tile
Processing
Clocks
Electronic equipment
Switches

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Suzuki, M., Hasegawa, Y., Tuan, V. M., Abe, S., & Amano, H. (2006). A cost-effective context memory structure for dynamically reconfigurable processors. In 20th International Parallel and Distributed Processing Symposium, IPDPS 2006 (Vol. 2006). [1639433] https://doi.org/10.1109/IPDPS.2006.1639433

A cost-effective context memory structure for dynamically reconfigurable processors. / Suzuki, Masayasu; Hasegawa, Yohei; Tuan, Vu Manh; Abe, Shohei; Amano, Hideharu.

20th International Parallel and Distributed Processing Symposium, IPDPS 2006. Vol. 2006 2006. 1639433.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Suzuki, M, Hasegawa, Y, Tuan, VM, Abe, S & Amano, H 2006, A cost-effective context memory structure for dynamically reconfigurable processors. in 20th International Parallel and Distributed Processing Symposium, IPDPS 2006. vol. 2006, 1639433. https://doi.org/10.1109/IPDPS.2006.1639433
Suzuki M, Hasegawa Y, Tuan VM, Abe S, Amano H. A cost-effective context memory structure for dynamically reconfigurable processors. In 20th International Parallel and Distributed Processing Symposium, IPDPS 2006. Vol. 2006. 2006. 1639433 https://doi.org/10.1109/IPDPS.2006.1639433
Suzuki, Masayasu ; Hasegawa, Yohei ; Tuan, Vu Manh ; Abe, Shohei ; Amano, Hideharu. / A cost-effective context memory structure for dynamically reconfigurable processors. 20th International Parallel and Distributed Processing Symposium, IPDPS 2006. Vol. 2006 2006.
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