A dynamic link-width optimization for network-on-chip

Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Network-on-Chip (NoC) is considered to be a promising approach to implement many-core systems and a large number of on-chip router optimization studies have been proposed. In this paper, we propose to dynamically adjust link-width of each port on a router optimized to spatially biased traffic. Different from the previous NoC optimization approaches, in which the optimization is almost performed in the NoC design step, the proposed method achieves a dynamical link-width optimization at run-time. Index Terms-Network-on-Chip, router architecture, traffic analysis

Original languageEnglish
Title of host publicationProceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011
Pages106-108
Number of pages3
Volume2
DOIs
Publication statusPublished - 2011
Event1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Co-located with the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011 - Toyama, Japan
Duration: 2011 Aug 282011 Aug 31

Other

Other1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Co-located with the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011
CountryJapan
CityToyama
Period11/8/2811/8/31

Fingerprint

Routers
Network-on-chip

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Networks and Communications

Cite this

Wang, D., Koibuchi, M., Yoneda, T., Matsutani, H., & Amano, H. (2011). A dynamic link-width optimization for network-on-chip. In Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011 (Vol. 2, pp. 106-108). [602900] https://doi.org/10.1109/RTCSA.2011.60

A dynamic link-width optimization for network-on-chip. / Wang, Daihan; Koibuchi, Michihiro; Yoneda, Tomohiro; Matsutani, Hiroki; Amano, Hideharu.

Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011. Vol. 2 2011. p. 106-108 602900.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wang, D, Koibuchi, M, Yoneda, T, Matsutani, H & Amano, H 2011, A dynamic link-width optimization for network-on-chip. in Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011. vol. 2, 602900, pp. 106-108, 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Co-located with the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011, Toyama, Japan, 11/8/28. https://doi.org/10.1109/RTCSA.2011.60
Wang D, Koibuchi M, Yoneda T, Matsutani H, Amano H. A dynamic link-width optimization for network-on-chip. In Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011. Vol. 2. 2011. p. 106-108. 602900 https://doi.org/10.1109/RTCSA.2011.60
Wang, Daihan ; Koibuchi, Michihiro ; Yoneda, Tomohiro ; Matsutani, Hiroki ; Amano, Hideharu. / A dynamic link-width optimization for network-on-chip. Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011. Vol. 2 2011. pp. 106-108
@inproceedings{95c562dcc06143c1bd21752a4e7c37f9,
title = "A dynamic link-width optimization for network-on-chip",
abstract = "Network-on-Chip (NoC) is considered to be a promising approach to implement many-core systems and a large number of on-chip router optimization studies have been proposed. In this paper, we propose to dynamically adjust link-width of each port on a router optimized to spatially biased traffic. Different from the previous NoC optimization approaches, in which the optimization is almost performed in the NoC design step, the proposed method achieves a dynamical link-width optimization at run-time. Index Terms-Network-on-Chip, router architecture, traffic analysis",
author = "Daihan Wang and Michihiro Koibuchi and Tomohiro Yoneda and Hiroki Matsutani and Hideharu Amano",
year = "2011",
doi = "10.1109/RTCSA.2011.60",
language = "English",
isbn = "9780769545028",
volume = "2",
pages = "106--108",
booktitle = "Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011",

}

TY - GEN

T1 - A dynamic link-width optimization for network-on-chip

AU - Wang, Daihan

AU - Koibuchi, Michihiro

AU - Yoneda, Tomohiro

AU - Matsutani, Hiroki

AU - Amano, Hideharu

PY - 2011

Y1 - 2011

N2 - Network-on-Chip (NoC) is considered to be a promising approach to implement many-core systems and a large number of on-chip router optimization studies have been proposed. In this paper, we propose to dynamically adjust link-width of each port on a router optimized to spatially biased traffic. Different from the previous NoC optimization approaches, in which the optimization is almost performed in the NoC design step, the proposed method achieves a dynamical link-width optimization at run-time. Index Terms-Network-on-Chip, router architecture, traffic analysis

AB - Network-on-Chip (NoC) is considered to be a promising approach to implement many-core systems and a large number of on-chip router optimization studies have been proposed. In this paper, we propose to dynamically adjust link-width of each port on a router optimized to spatially biased traffic. Different from the previous NoC optimization approaches, in which the optimization is almost performed in the NoC design step, the proposed method achieves a dynamical link-width optimization at run-time. Index Terms-Network-on-Chip, router architecture, traffic analysis

UR - http://www.scopus.com/inward/record.url?scp=84862943175&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84862943175&partnerID=8YFLogxK

U2 - 10.1109/RTCSA.2011.60

DO - 10.1109/RTCSA.2011.60

M3 - Conference contribution

SN - 9780769545028

VL - 2

SP - 106

EP - 108

BT - Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011

ER -