A dynamic offset control technique for comparator design in scaled CMOS technology

Xiaolei Zhu; Yanfei Chen; Masaya Kibune; Yasumoto Tomita; Takayuki Hamada; Hirotaka Tamura; Sanroku Tsukamoto; Tadahiro Kuroda

doi:10.1109/CICC.2008.4672130

A dynamic offset control technique for comparator design in scaled CMOS technology

Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda

Research output: Contribution to journal › Conference article › peer-review

12 Citations (Scopus)

Abstract

A principle of charge compensation approach for comparator offset control is analyzed. A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 × 65 μm² and consumes 380 μW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.

Original language	English
Article number	4672130
Pages (from-to)	495-498
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.2008.4672130
Publication status	Published - 2008
Event	IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States Duration: 2008 Sept 21 → 2008 Sept 24

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/CICC.2008.4672130

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title = "A dynamic offset control technique for comparator design in scaled CMOS technology",

abstract = "A principle of charge compensation approach for comparator offset control is analyzed. A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 × 65 μm2 and consumes 380 μW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.",

author = "Xiaolei Zhu and Yanfei Chen and Masaya Kibune and Yasumoto Tomita and Takayuki Hamada and Hirotaka Tamura and Sanroku Tsukamoto and Tadahiro Kuroda",

year = "2008",

doi = "10.1109/CICC.2008.4672130",

language = "English",

pages = "495--498",

journal = "Proceedings of the Custom Integrated Circuits Conference",

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note = "IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 ; Conference date: 21-09-2008 Through 24-09-2008",

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T1 - A dynamic offset control technique for comparator design in scaled CMOS technology

AU - Zhu, Xiaolei

AU - Chen, Yanfei

AU - Kibune, Masaya

AU - Tomita, Yasumoto

AU - Hamada, Takayuki

AU - Tamura, Hirotaka

AU - Tsukamoto, Sanroku

AU - Kuroda, Tadahiro

PY - 2008

Y1 - 2008

N2 - A principle of charge compensation approach for comparator offset control is analyzed. A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 × 65 μm2 and consumes 380 μW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.

AB - A principle of charge compensation approach for comparator offset control is analyzed. A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 × 65 μm2 and consumes 380 μW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.

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U2 - 10.1109/CICC.2008.4672130

DO - 10.1109/CICC.2008.4672130

M3 - Conference article

AN - SCOPUS:57849102144

SN - 0886-5930

SP - 495

EP - 498

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

M1 - 4672130

T2 - IEEE 2008 Custom Integrated Circuits Conference, CICC 2008

Y2 - 21 September 2008 through 24 September 2008

ER -

A dynamic offset control technique for comparator design in scaled CMOS technology

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