A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA

Akihito Tsusaka; Mai Izawa; Rie Uno; Nobuyuki Ozaki; Hideharu Amano

doi:10.1109/FPL.2013.6645594

A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA

Akihito Tsusaka, Mai Izawa, Rie Uno, Nobuyuki Ozaki, Hideharu Amano

Department of Information and Computer Science

Research output: Contribution to conference › Paper › peer-review

1 Citation (Scopus)

Abstract

Cool Mega Array (CMA) is an energy efficient Coarse Grained Reconfigurable processor Array (CGRA) consisting of a large PE (Processing Element) array. In order to reduce the power for storing intermediate results and clock tree, the PE array is consisting of combinatorial circuits. A hardware completion detection mechanism for CMA is proposed, implemented and evaluated. Each PE uses serially connected buffers with selectable taps, and the delay is decided according to the operation executed in the PE. Since the completion signal is transferred exactly on the same paths that for computation, the delay in the switch and wires are accounted. The post layout simulation revealed that the same performance without the mechanism can be obtained only with 5.1% area overhead and less than 6% extra power consumption. With the mechanism, a single micro-code can be used for various supply voltages to PE array.

Original language	English
DOIs	https://doi.org/10.1109/FPL.2013.6645594
Publication status	Published - 2013 Jan 1
Event	2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Porto, Portugal Duration: 2013 Sept 2 → 2013 Sept 4

Other

Other	2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013
Country/Territory	Portugal
City	Porto
Period	13/9/2 → 13/9/4

ASJC Scopus subject areas

Computational Theory and Mathematics
Applied Mathematics

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10.1109/FPL.2013.6645594

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@conference{2f39702d4b9248ac8c4ba2847ad48526,

title = "A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA",

abstract = "Cool Mega Array (CMA) is an energy efficient Coarse Grained Reconfigurable processor Array (CGRA) consisting of a large PE (Processing Element) array. In order to reduce the power for storing intermediate results and clock tree, the PE array is consisting of combinatorial circuits. A hardware completion detection mechanism for CMA is proposed, implemented and evaluated. Each PE uses serially connected buffers with selectable taps, and the delay is decided according to the operation executed in the PE. Since the completion signal is transferred exactly on the same paths that for computation, the delay in the switch and wires are accounted. The post layout simulation revealed that the same performance without the mechanism can be obtained only with 5.1% area overhead and less than 6% extra power consumption. With the mechanism, a single micro-code can be used for various supply voltages to PE array.",

author = "Akihito Tsusaka and Mai Izawa and Rie Uno and Nobuyuki Ozaki and Hideharu Amano",

year = "2013",

month = jan,

day = "1",

doi = "10.1109/FPL.2013.6645594",

language = "English",

note = "2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 ; Conference date: 02-09-2013 Through 04-09-2013",

}

TY - CONF

T1 - A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA

AU - Tsusaka, Akihito

AU - Izawa, Mai

AU - Uno, Rie

AU - Ozaki, Nobuyuki

AU - Amano, Hideharu

PY - 2013/1/1

Y1 - 2013/1/1

N2 - Cool Mega Array (CMA) is an energy efficient Coarse Grained Reconfigurable processor Array (CGRA) consisting of a large PE (Processing Element) array. In order to reduce the power for storing intermediate results and clock tree, the PE array is consisting of combinatorial circuits. A hardware completion detection mechanism for CMA is proposed, implemented and evaluated. Each PE uses serially connected buffers with selectable taps, and the delay is decided according to the operation executed in the PE. Since the completion signal is transferred exactly on the same paths that for computation, the delay in the switch and wires are accounted. The post layout simulation revealed that the same performance without the mechanism can be obtained only with 5.1% area overhead and less than 6% extra power consumption. With the mechanism, a single micro-code can be used for various supply voltages to PE array.

AB - Cool Mega Array (CMA) is an energy efficient Coarse Grained Reconfigurable processor Array (CGRA) consisting of a large PE (Processing Element) array. In order to reduce the power for storing intermediate results and clock tree, the PE array is consisting of combinatorial circuits. A hardware completion detection mechanism for CMA is proposed, implemented and evaluated. Each PE uses serially connected buffers with selectable taps, and the delay is decided according to the operation executed in the PE. Since the completion signal is transferred exactly on the same paths that for computation, the delay in the switch and wires are accounted. The post layout simulation revealed that the same performance without the mechanism can be obtained only with 5.1% area overhead and less than 6% extra power consumption. With the mechanism, a single micro-code can be used for various supply voltages to PE array.

UR - http://www.scopus.com/inward/record.url?scp=84898653076&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84898653076&partnerID=8YFLogxK

U2 - 10.1109/FPL.2013.6645594

DO - 10.1109/FPL.2013.6645594

M3 - Paper

AN - SCOPUS:84898653076

T2 - 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013

Y2 - 2 September 2013 through 4 September 2013

ER -

A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA

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