A high speed design and implementation of dynamically reconfigurable processor using 28NM SOI technology

Toru Katagiri, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Although dynamically reconfigurable processor arrays (DRPAs) are advantageous for embedded devices because of their high energy efficiency, many of the recent mobile devices are required to execute increasingly performance-centric jobs. One fairly straingtfoward way of increasing the clock frequency is introducing a pipelined structure into each PE. However, this results in frequent pipeline stalls due to the data hazard between multiple PEs. In order to mitigate the effect of data hazard between PEs, we propose a tiny vector instruction mechanism. With a single vector instruction, a small amount of data is continuously processed in the pipeline of the PE. Pipeline stalls are removed without increasing the number of hardware contexts, and thus the amount of configuration data. Evaluation results based on the implementation using 28nm SOI process technology, a DRPA with tiny vector instructions (DRPA-TVI) improves the performance by 2.4 three times compared to a base DRPA with just a small increase of area and power consumption.

Original languageEnglish
Title of host publicationConference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9783000446450
DOIs
Publication statusPublished - 2014 Oct 16
Event24th International Conference on Field Programmable Logic and Applications, FPL 2014 - Munich, Germany
Duration: 2014 Sep 12014 Sep 5

Publication series

NameConference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014

Other

Other24th International Conference on Field Programmable Logic and Applications, FPL 2014
CountryGermany
CityMunich
Period14/9/114/9/5

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture

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