A high speed license plate recognition system on an FPGA

Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A high speed FPGA off-loading engine for detecting the license plate itself in order to avoid the traffic accident is proposed. A complicated algorithm is written in Handel-C, and parallel processing is explicitly utilized in every level of implementation; an input image is segmented into 16 areas, and each area is processed in parallel by a multiple calculation unit executing pipeline processing and a distributed memory module. A pro-totype circuit implemented on a general purpose FPGA board achieved 4.16 times performance as software execution on a Pentium-Ill desktop PC. The highest performance in literature; 100 frames per second; can be achieved.

Original languageEnglish
Title of host publicationProceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
Pages554-557
Number of pages4
DOIs
Publication statusPublished - 2007
Event2007 International Conference on Field Programmable Logic and Applications, FPL - Amsterdam, Netherlands
Duration: 2007 Aug 272007 Aug 29

Other

Other2007 International Conference on Field Programmable Logic and Applications, FPL
CountryNetherlands
CityAmsterdam
Period07/8/2707/8/29

Fingerprint

Field programmable gate arrays (FPGA)
Highway accidents
Processing
Pipelines
Engines
Data storage equipment
Networks (circuits)

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Kanamori, T., Amano, H., Arai, M., Konno, D., Nanba, T., & Ajioka, Y. (2007). A high speed license plate recognition system on an FPGA. In Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL (pp. 554-557). [4380715] https://doi.org/10.1109/FPL.2007.4380715

A high speed license plate recognition system on an FPGA. / Kanamori, Takamasa; Amano, Hideharu; Arai, Masatoshi; Konno, Daisuke; Nanba, Tomomichi; Ajioka, Yoshiaki.

Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. 2007. p. 554-557 4380715.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kanamori, T, Amano, H, Arai, M, Konno, D, Nanba, T & Ajioka, Y 2007, A high speed license plate recognition system on an FPGA. in Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL., 4380715, pp. 554-557, 2007 International Conference on Field Programmable Logic and Applications, FPL, Amsterdam, Netherlands, 07/8/27. https://doi.org/10.1109/FPL.2007.4380715
Kanamori T, Amano H, Arai M, Konno D, Nanba T, Ajioka Y. A high speed license plate recognition system on an FPGA. In Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. 2007. p. 554-557. 4380715 https://doi.org/10.1109/FPL.2007.4380715
Kanamori, Takamasa ; Amano, Hideharu ; Arai, Masatoshi ; Konno, Daisuke ; Nanba, Tomomichi ; Ajioka, Yoshiaki. / A high speed license plate recognition system on an FPGA. Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. 2007. pp. 554-557
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