A link removal methodology for networks-on-chip on reconfigurable systems

Daihan Wang, Hiroki Matsutani, Hideharu Arnano, Michihiro Koibuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

While the regular 2-D mesh topology has been utilized for most of Network-on-Chips (NoCs) on FPGAs, spatially biased traffic in some applications make some customization method feasible. A link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize required hardware amount. Based on the pre-analyzed traffic information, links on which the communication amount is small are removed to reduce the hardware cost with enough performance being kept. Two policies are proposed to avoid deadlocks and better performance can be achieved compared with up*/down* routing on the irregular topology with links removed. In the image recognition application susan, the proposed method can save 30% of the hardware amount without performance degradation.

Original languageEnglish
Title of host publicationProceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL
Pages269-274
Number of pages6
DOIs
Publication statusPublished - 2008
Event2008 International Conference on Field Programmable Logic and Applications, FPL - Heidelberg, Germany
Duration: 2008 Sep 82008 Sep 10

Other

Other2008 International Conference on Field Programmable Logic and Applications, FPL
CountryGermany
CityHeidelberg
Period08/9/808/9/10

Fingerprint

Hardware
Topology
Image recognition
Routers
Field programmable gate arrays (FPGA)
Degradation
Communication
Network-on-chip
Costs

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Wang, D., Matsutani, H., Arnano, H., & Koibuchi, M. (2008). A link removal methodology for networks-on-chip on reconfigurable systems. In Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL (pp. 269-274). [4629943] https://doi.org/10.1109/FPL.2008.4629943

A link removal methodology for networks-on-chip on reconfigurable systems. / Wang, Daihan; Matsutani, Hiroki; Arnano, Hideharu; Koibuchi, Michihiro.

Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. 2008. p. 269-274 4629943.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wang, D, Matsutani, H, Arnano, H & Koibuchi, M 2008, A link removal methodology for networks-on-chip on reconfigurable systems. in Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL., 4629943, pp. 269-274, 2008 International Conference on Field Programmable Logic and Applications, FPL, Heidelberg, Germany, 08/9/8. https://doi.org/10.1109/FPL.2008.4629943
Wang D, Matsutani H, Arnano H, Koibuchi M. A link removal methodology for networks-on-chip on reconfigurable systems. In Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. 2008. p. 269-274. 4629943 https://doi.org/10.1109/FPL.2008.4629943
Wang, Daihan ; Matsutani, Hiroki ; Arnano, Hideharu ; Koibuchi, Michihiro. / A link removal methodology for networks-on-chip on reconfigurable systems. Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. 2008. pp. 269-274
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