A low-power fault-tolerant noc using error correction and detection codes

Yu Kojima, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Power consumption and reliability become two crucial factors in designing Network-on-Chip (NoC) for modern chip multiprocessors. In this paper, we present a lowpower fault-tolerant NoC architecture by using error correction and detection codes in order to reduce the supply voltage, while the bit error rate of the end-to-end on-chip communication is maintained. The method aims to optimize the power consumption of a given NoC by selecting the best fault-tolerant technique. Simulation results show that our error detection/correction techniques greatly reduce the number of re-transmitted packets due to soft errors. These techniques also reduce up to 40% of flit transmission energy compared to the original NoC without any fault-tolerant techniques. We show that control information of each packet (e.g., destination address) should be protected first by using a high-reliable error detection or correction technique when the error rate is high.

Original languageEnglish
Title of host publicationProceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010
Pages111-118
Number of pages8
Publication statusPublished - 2010
Event9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010 - Innsbruck, Austria
Duration: 2010 Feb 162010 Feb 18

Other

Other9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010
CountryAustria
CityInnsbruck
Period10/2/1610/2/18

Fingerprint

Error detection
Error correction
Electric power utilization
Bit error rate
Network-on-chip
Communication
Electric potential

Keywords

  • Fault tolerance
  • Network-on-chip
  • Power consumption
  • Soft error

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Networks and Communications
  • Software

Cite this

Kojima, Y., Matsutani, H., Koibuchi, M., & Amano, H. (2010). A low-power fault-tolerant noc using error correction and detection codes. In Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010 (pp. 111-118)

A low-power fault-tolerant noc using error correction and detection codes. / Kojima, Yu; Matsutani, Hiroki; Koibuchi, Michihiro; Amano, Hideharu.

Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. 2010. p. 111-118.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kojima, Y, Matsutani, H, Koibuchi, M & Amano, H 2010, A low-power fault-tolerant noc using error correction and detection codes. in Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. pp. 111-118, 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010, Innsbruck, Austria, 10/2/16.
Kojima Y, Matsutani H, Koibuchi M, Amano H. A low-power fault-tolerant noc using error correction and detection codes. In Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. 2010. p. 111-118
Kojima, Yu ; Matsutani, Hiroki ; Koibuchi, Michihiro ; Amano, Hideharu. / A low-power fault-tolerant noc using error correction and detection codes. Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. 2010. pp. 111-118
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