A low power NoC router using the marching memory through type

Ryota Yasudo; Takahiro Kagami; Hideharu Amano; Yasunobu Nakase; Masashi Watanebe; Tsukasa Oishi; Toru Shimizu; Tadao Nakamura

doi:10.1109/CoolChips.2014.6842960

A low power NoC router using the marching memory through type

Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanebe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We have concluded that with a router using MMTH the power consumption is associated with the bit change rate of the data, and when NAS parallel benchmarks work on NoC, it is reduced by 42.4% on average at 2GHz compared with a traditional FIFO implementation. The performance degradation caused by the delay of the reading time can be mostly saved by the look-ahead technique in the router.

Original language	English
Title of host publication	IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII
Publisher	IEEE Computer Society
ISBN (Print)	9781479938094
DOIs	https://doi.org/10.1109/CoolChips.2014.6842960
Publication status	Published - 2014
Event	17th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2014 - Yokohama, Japan Duration: 2014 Apr 14 → 2014 Apr 16

Publication series

Name	IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII

Other

Other	17th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2014
Country/Territory	Japan
City	Yokohama
Period	14/4/14 → 14/4/16

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CoolChips.2014.6842960

Cite this

Yasudo, R., Kagami, T., Amano, H., Nakase, Y., Watanebe, M., Oishi, T., Shimizu, T., & Nakamura, T. (2014). A low power NoC router using the marching memory through type. In IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII [6842960] (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII). IEEE Computer Society. https://doi.org/10.1109/CoolChips.2014.6842960

A low power NoC router using the marching memory through type. / Yasudo, Ryota; Kagami, Takahiro; Amano, Hideharu et al.

IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII. IEEE Computer Society, 2014. 6842960 (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yasudo, R, Kagami, T, Amano, H, Nakase, Y, Watanebe, M, Oishi, T, Shimizu, T & Nakamura, T 2014, A low power NoC router using the marching memory through type. in IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII., 6842960, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII, IEEE Computer Society, 17th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2014, Yokohama, Japan, 14/4/14. https://doi.org/10.1109/CoolChips.2014.6842960

Yasudo R, Kagami T, Amano H, Nakase Y, Watanebe M, Oishi T et al. A low power NoC router using the marching memory through type. In IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII. IEEE Computer Society. 2014. 6842960. (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII). doi: 10.1109/CoolChips.2014.6842960

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A low power NoC router using the marching memory through type

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