A low-power third-order ΔΣ modulator using ring amplifiers with power-saving technique

Alexis Gryta, Takuma Suguro, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a ΔΣ modulator with ring amplifiers to decrease the power consumption. The proposed ΔΣ modulator employs a technique of cutting-off the current of ring amplifiers after they are settled in each clock cycle. The optimum cutting-off timing can be determined by monitoring the output SNDR. The proposed 1-bit third-order ΔΣ modulator was designed in 65-nm CMOS process. From schematic-level circuit simulation, 76-dB SNDR was obtained at signal bandwidth of 1 MHz and clock frequency of 128 MHz. More than 40% percent of the power is saved at clock frequency of 128 MHz and power scalability is obtained.

Original languageEnglish
Title of host publication2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages275-278
Number of pages4
ISBN (Electronic)9781509018307
DOIs
Publication statusPublished - 2016 Dec 15
Event2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016 - Hong Kong, Hong Kong
Duration: 2016 Aug 32016 Aug 5

Other

Other2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
CountryHong Kong
CityHong Kong
Period16/8/316/8/5

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Keywords

  • delta-sigma modulator
  • low power
  • ring amplifier

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Gryta, A., Suguro, T., & Ishikuro, H. (2016). A low-power third-order ΔΣ modulator using ring amplifiers with power-saving technique. In 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016 (pp. 275-278). [7785261] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2016.7785261