A low-power third-order ΔΣ modulator using ring amplifiers with power-saving technique

Alexis Gryta; Takuma Suguro; Hiroki Ishikuro

doi:10.1109/EDSSC.2016.7785261

A low-power third-order ΔΣ modulator using ring amplifiers with power-saving technique

Alexis Gryta, Takuma Suguro, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents a ΔΣ modulator with ring amplifiers to decrease the power consumption. The proposed ΔΣ modulator employs a technique of cutting-off the current of ring amplifiers after they are settled in each clock cycle. The optimum cutting-off timing can be determined by monitoring the output SNDR. The proposed 1-bit third-order ΔΣ modulator was designed in 65-nm CMOS process. From schematic-level circuit simulation, 76-dB SNDR was obtained at signal bandwidth of 1 MHz and clock frequency of 128 MHz. More than 40% percent of the power is saved at clock frequency of 128 MHz and power scalability is obtained.

Original language	English
Title of host publication	2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	275-278
Number of pages	4
ISBN (Electronic)	9781509018307
DOIs	https://doi.org/10.1109/EDSSC.2016.7785261
Publication status	Published - 2016 Dec 15
Event	2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016 - Hong Kong, Hong Kong Duration: 2016 Aug 3 → 2016 Aug 5

Other

Other	2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
Country/Territory	Hong Kong
City	Hong Kong
Period	16/8/3 → 16/8/5

Keywords

delta-sigma modulator
low power
ring amplifier

ASJC Scopus subject areas

Electrical and Electronic Engineering
Hardware and Architecture

Access to Document

10.1109/EDSSC.2016.7785261

Cite this

A low-power third-order ΔΣ modulator using ring amplifiers with power-saving technique. / Gryta, Alexis; Suguro, Takuma; Ishikuro, Hiroki.

2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 275-278 7785261.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Gryta, A, Suguro, T & Ishikuro, H 2016, A low-power third-order ΔΣ modulator using ring amplifiers with power-saving technique. in 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016., 7785261, Institute of Electrical and Electronics Engineers Inc., pp. 275-278, 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016, Hong Kong, Hong Kong, 16/8/3. https://doi.org/10.1109/EDSSC.2016.7785261

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title = "A low-power third-order ΔΣ modulator using ring amplifiers with power-saving technique",

abstract = "This paper presents a ΔΣ modulator with ring amplifiers to decrease the power consumption. The proposed ΔΣ modulator employs a technique of cutting-off the current of ring amplifiers after they are settled in each clock cycle. The optimum cutting-off timing can be determined by monitoring the output SNDR. The proposed 1-bit third-order ΔΣ modulator was designed in 65-nm CMOS process. From schematic-level circuit simulation, 76-dB SNDR was obtained at signal bandwidth of 1 MHz and clock frequency of 128 MHz. More than 40% percent of the power is saved at clock frequency of 128 MHz and power scalability is obtained.",

keywords = "delta-sigma modulator, low power, ring amplifier",

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N2 - This paper presents a ΔΣ modulator with ring amplifiers to decrease the power consumption. The proposed ΔΣ modulator employs a technique of cutting-off the current of ring amplifiers after they are settled in each clock cycle. The optimum cutting-off timing can be determined by monitoring the output SNDR. The proposed 1-bit third-order ΔΣ modulator was designed in 65-nm CMOS process. From schematic-level circuit simulation, 76-dB SNDR was obtained at signal bandwidth of 1 MHz and clock frequency of 128 MHz. More than 40% percent of the power is saved at clock frequency of 128 MHz and power scalability is obtained.

AB - This paper presents a ΔΣ modulator with ring amplifiers to decrease the power consumption. The proposed ΔΣ modulator employs a technique of cutting-off the current of ring amplifiers after they are settled in each clock cycle. The optimum cutting-off timing can be determined by monitoring the output SNDR. The proposed 1-bit third-order ΔΣ modulator was designed in 65-nm CMOS process. From schematic-level circuit simulation, 76-dB SNDR was obtained at signal bandwidth of 1 MHz and clock frequency of 128 MHz. More than 40% percent of the power is saved at clock frequency of 128 MHz and power scalability is obtained.

KW - delta-sigma modulator

KW - low power

KW - ring amplifier

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BT - 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016

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ER -

A low-power third-order ΔΣ modulator using ring amplifiers with power-saving technique

Abstract

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Keywords

ASJC Scopus subject areas

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