A mapping method for multi-process execution on dynamically reconfigurable processors

Vu Manh Tuan, Hideharu Amano

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

The multi-process execution in dynamically reconfig-urable processors is a technique to enhance throughput by trying to exploit more inherent parallelism of applications. Basically, a total process for an application is divided into small processes, assigned into limited areas of a reconfigurable array, and concurrently executed in a pipelined manner. In order to improve the efficiency of the multi-process execution, a systematic method for mapping processes onto a reconfigurable array consisting of multiple hardware execution units is essential. This paper proposes and investigates a systematic method for mapping an application modeled as a Kahn Process Network onto a dynamically reconfigurable processing array. In order to execute streaming applications in a pipelined manner, the size of Tiles, which is a unit area of dynamically reconfigurable array, and the grouping of processes are adjusted. Using real applications such as DCT, JPEG encoder and Turbo encoder, the impact of different versions mapped onto the NEC Dynamically Reconfigurable Processor on performance is evaluated. Evaluation results show that our proposed mapping algorithm achieves the best performance in terms of the throughput and the execution time.

Original languageEnglish
Pages (from-to)2312-2322
Number of pages11
JournalIEICE Transactions on Information and Systems
VolumeE91-D
Issue number9
DOIs
Publication statusPublished - 2008 Sep

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Throughput
Array processing
Tile
Hardware

Keywords

  • Dynamically reconfigurable processor
  • Multi-process execution
  • Single-process execution

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Software
  • Artificial Intelligence
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition

Cite this

A mapping method for multi-process execution on dynamically reconfigurable processors. / Manh Tuan, Vu; Amano, Hideharu.

In: IEICE Transactions on Information and Systems, Vol. E91-D, No. 9, 09.2008, p. 2312-2322.

Research output: Contribution to journalArticle

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