Abstract
In a preemptive multitasking environment, when a task is preempted, necessary state information must be correctly preserved in order for the task to be resumed later. For hardware tasks executing on a coarse-grained dynamically reconfigurable processing array (DRPA), a greate amount of state data are usually distributed on many different storage elements. Besides, DRPAs have different architectures using a variety of development tools. This paper addresses such problems and propose a method for capturing the state data of hardware tasks. Based on resource usage analysis, algorithms for identifying preemption points and inserting preemption states subject to user-specified preemption latency are proposed. Also, the integaration of the proposed steps into the system design flow is discussed. The performance degradation caused by preemption is minimized by allowing preemption only at predefined points where demanded resources are small. The evaluation result using a model based on NEC Electronics DRP-1 shows that the proposed method could allow preemption for a certain task satisfying a given preemption latency with reasonable hardware overhead (from 6% to 15%).
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008 |
| Pages | 208-214 |
| Number of pages | 7 |
| Publication status | Published - 2008 |
| Event | 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008 - Las Vegas, NV, United States Duration: 2008 Jul 14 → 2008 Jul 17 |
Other
| Other | 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008 |
|---|---|
| Country | United States |
| City | Las Vegas, NV |
| Period | 08/7/14 → 08/7/17 |
Fingerprint
Keywords
- Dynamically reconfigurable processor
- Hardware overhead
- Preemption algorithm
- Preemption latency
ASJC Scopus subject areas
- Computer Science Applications
- Hardware and Architecture
- Software
Cite this
A method for capturing state data on dynamically reconfigurable processors. / Tuan, Vu Manh; Amano, Hideharu.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. 2008. p. 208-214.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A method for capturing state data on dynamically reconfigurable processors
AU - Tuan, Vu Manh
AU - Amano, Hideharu
PY - 2008
Y1 - 2008
N2 - In a preemptive multitasking environment, when a task is preempted, necessary state information must be correctly preserved in order for the task to be resumed later. For hardware tasks executing on a coarse-grained dynamically reconfigurable processing array (DRPA), a greate amount of state data are usually distributed on many different storage elements. Besides, DRPAs have different architectures using a variety of development tools. This paper addresses such problems and propose a method for capturing the state data of hardware tasks. Based on resource usage analysis, algorithms for identifying preemption points and inserting preemption states subject to user-specified preemption latency are proposed. Also, the integaration of the proposed steps into the system design flow is discussed. The performance degradation caused by preemption is minimized by allowing preemption only at predefined points where demanded resources are small. The evaluation result using a model based on NEC Electronics DRP-1 shows that the proposed method could allow preemption for a certain task satisfying a given preemption latency with reasonable hardware overhead (from 6% to 15%).
AB - In a preemptive multitasking environment, when a task is preempted, necessary state information must be correctly preserved in order for the task to be resumed later. For hardware tasks executing on a coarse-grained dynamically reconfigurable processing array (DRPA), a greate amount of state data are usually distributed on many different storage elements. Besides, DRPAs have different architectures using a variety of development tools. This paper addresses such problems and propose a method for capturing the state data of hardware tasks. Based on resource usage analysis, algorithms for identifying preemption points and inserting preemption states subject to user-specified preemption latency are proposed. Also, the integaration of the proposed steps into the system design flow is discussed. The performance degradation caused by preemption is minimized by allowing preemption only at predefined points where demanded resources are small. The evaluation result using a model based on NEC Electronics DRP-1 shows that the proposed method could allow preemption for a certain task satisfying a given preemption latency with reasonable hardware overhead (from 6% to 15%).
KW - Dynamically reconfigurable processor
KW - Hardware overhead
KW - Preemption algorithm
KW - Preemption latency
UR - http://www.scopus.com/inward/record.url?scp=62649129709&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=62649129709&partnerID=8YFLogxK
M3 - Conference contribution
SN - 1601320647
SN - 9781601320643
SP - 208
EP - 214
BT - Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008
ER -