A multilevel NOSQL cache design combining In-NIC and In-Kernel caches

Yuta Tokusashi, Hiroki Matsutani

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

Since a large-scale in-memory data store, such as key-value store (KVS), is an important software platform for data centers, this paper focuses on an FPGA-based custom hardware to further improve the efficiency of KVS. Although such FPGA-based KVS accelerators have been studied and shown a high performance per Watt compared to software-based processing, since their cache capacity is strictly limited by the DRAMs implemented on FPGA boards, their application domain is also limited. To address this issue, in this paper, we propose a multilevel NOSQL cache architecture that utilizes both the FPGA-based hardware cache and an in-kernel software cache in a complementary style. They are referred as L1 and L2 NOSQL caches, respectively. The proposed multilevel NOSQL cache architecture motivates us to explore various design options, such as cache write and inclusion policies between L1 and L2 NOSQL caches. We implemented a prototype system of the proposed multilevel NOSQL cache using NetFPGA-10G board and Linux Netfilter framework. Based on the prototype implementation, we explore the various design options for the multilevel NOSQL caches. Simulation results show that our multilevel NOSQL cache design reduces the cache miss ratio and improves the throughput compared to the non-hierarchical design.

Original languageEnglish
Title of host publicationProceedings - 2016 IEEE 24th Annual Symposium on High-Performance Interconnects, HOTI 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages60-67
Number of pages8
ISBN (Electronic)9781509028542
DOIs
Publication statusPublished - 2016 Dec 28
Event24th IEEE Annual Symposium on High-Performance Interconnects, HOTI 2016 - Santa Clara, United States
Duration: 2016 Aug 242016 Aug 26

Other

Other24th IEEE Annual Symposium on High-Performance Interconnects, HOTI 2016
CountryUnited States
CitySanta Clara
Period16/8/2416/8/26

Fingerprint

Field programmable gate arrays (FPGA)
Hardware
Dynamic random access storage
Particle accelerators
Throughput
Data storage equipment
Processing

Keywords

  • FPGA
  • Key-value store
  • Multilevel cache
  • NOSQL

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications

Cite this

Tokusashi, Y., & Matsutani, H. (2016). A multilevel NOSQL cache design combining In-NIC and In-Kernel caches. In Proceedings - 2016 IEEE 24th Annual Symposium on High-Performance Interconnects, HOTI 2016 (pp. 60-67). [7801439] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/HOTI.2016.022

A multilevel NOSQL cache design combining In-NIC and In-Kernel caches. / Tokusashi, Yuta; Matsutani, Hiroki.

Proceedings - 2016 IEEE 24th Annual Symposium on High-Performance Interconnects, HOTI 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 60-67 7801439.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tokusashi, Y & Matsutani, H 2016, A multilevel NOSQL cache design combining In-NIC and In-Kernel caches. in Proceedings - 2016 IEEE 24th Annual Symposium on High-Performance Interconnects, HOTI 2016., 7801439, Institute of Electrical and Electronics Engineers Inc., pp. 60-67, 24th IEEE Annual Symposium on High-Performance Interconnects, HOTI 2016, Santa Clara, United States, 16/8/24. https://doi.org/10.1109/HOTI.2016.022
Tokusashi Y, Matsutani H. A multilevel NOSQL cache design combining In-NIC and In-Kernel caches. In Proceedings - 2016 IEEE 24th Annual Symposium on High-Performance Interconnects, HOTI 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 60-67. 7801439 https://doi.org/10.1109/HOTI.2016.022
Tokusashi, Yuta ; Matsutani, Hiroki. / A multilevel NOSQL cache design combining In-NIC and In-Kernel caches. Proceedings - 2016 IEEE 24th Annual Symposium on High-Performance Interconnects, HOTI 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 60-67
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