A Near-Optimum 13.56 MHz CMOS Active Rectifier With Circuit-Delay Real-Time Calibrations for High-Current Biomedical Implants

Cheng Huang, Toru Kawajiri, Hiroki Ishikuro

Research output: Contribution to journalArticle

27 Citations (Scopus)

Abstract

In this paper, a near-optimum active rectifier is proposed to achieve well-optimized power conversion efficiency (PCE) and voltage conversion ratio (VCR) under various process, voltage, temperature (PVT) and loading conditions. The near-optimum operation includes: eliminated reverse current loss and maximized conduction time achieved by the proposed sampling-based real-time calibrations with automatic circuit-delay compensation for both on- and off-time of active diodes considering PVT variations; and power stage optimizations with adaptive sizing over a wide loading range. The design is fabricated in TSMC 65 nm process with standard I/O devices. Measurement results show more than 36% and 17% improvement in PCE and VCR, respectively, by the proposed techniques. A peak PCE of 94.8% with an 80 Ω loading, a peak VCR of 98.7% with 1 kΩ loading, and a maximum output power of 248.1 mW are achieved with 2.5 V input amplitude.

Original languageEnglish
JournalIEEE Journal of Solid-State Circuits
DOIs
Publication statusAccepted/In press - 2016 Jul 13

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Delay circuits
Calibration
Conversion efficiency
Electric potential
Diodes
Sampling
Temperature

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

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title = "A Near-Optimum 13.56 MHz CMOS Active Rectifier With Circuit-Delay Real-Time Calibrations for High-Current Biomedical Implants",
abstract = "In this paper, a near-optimum active rectifier is proposed to achieve well-optimized power conversion efficiency (PCE) and voltage conversion ratio (VCR) under various process, voltage, temperature (PVT) and loading conditions. The near-optimum operation includes: eliminated reverse current loss and maximized conduction time achieved by the proposed sampling-based real-time calibrations with automatic circuit-delay compensation for both on- and off-time of active diodes considering PVT variations; and power stage optimizations with adaptive sizing over a wide loading range. The design is fabricated in TSMC 65 nm process with standard I/O devices. Measurement results show more than 36{\%} and 17{\%} improvement in PCE and VCR, respectively, by the proposed techniques. A peak PCE of 94.8{\%} with an 80 Ω loading, a peak VCR of 98.7{\%} with 1 kΩ loading, and a maximum output power of 248.1 mW are achieved with 2.5 V input amplitude.",
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