### Abstract

A new design scheme for logic circuits utilizing single electron transistors (SETs) is proposed. First, logic operations are implemented in logic trees composed of SETs used as pull-down devices. Second, the supply voltage to SET logic trees is lower than the gate voltage swing of SETs. Third, a clock control concept similar to that of complementary metal-oxide-semiconductor (CMOS) dynamic logic is utilized. Finally, the output voltages of logic trees are amplified to the same voltage as the gate voltage swing of SETs by the CMOS inverters in order to drive the next gates. It is confirmed by the hybrid simulator of single electron tunneling and SPICE that a SET logic circuit, a four-way exclusive OR, operates perfectly. It is concluded that the proposed SET logic is consistent in voltage levels and is realistic for the hybrid circuits of SETs and CMOS.

Original language | English |
---|---|

Pages (from-to) | 4027-4032 |

Number of pages | 6 |

Journal | Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers |

Volume | 38 |

Issue number | 7 B |

Publication status | Published - 1999 Jul 15 |

Externally published | Yes |

### Fingerprint

### Keywords

- CMOS
- Coulomb blockade
- Dynamic logic circuits
- MOSFET
- SET
- Single electron tunneling

### ASJC Scopus subject areas

- Physics and Astronomy (miscellaneous)

### Cite this

*Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers*,

*38*(7 B), 4027-4032.

**A new design scheme for logic circuits with single electron transistors.** / Uchida, Ken; Matsuzawa, Kazuya; Toriumi, Akira.

Research output: Contribution to journal › Article

*Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers*, vol. 38, no. 7 B, pp. 4027-4032.

}

TY - JOUR

T1 - A new design scheme for logic circuits with single electron transistors

AU - Uchida, Ken

AU - Matsuzawa, Kazuya

AU - Toriumi, Akira

PY - 1999/7/15

Y1 - 1999/7/15

N2 - A new design scheme for logic circuits utilizing single electron transistors (SETs) is proposed. First, logic operations are implemented in logic trees composed of SETs used as pull-down devices. Second, the supply voltage to SET logic trees is lower than the gate voltage swing of SETs. Third, a clock control concept similar to that of complementary metal-oxide-semiconductor (CMOS) dynamic logic is utilized. Finally, the output voltages of logic trees are amplified to the same voltage as the gate voltage swing of SETs by the CMOS inverters in order to drive the next gates. It is confirmed by the hybrid simulator of single electron tunneling and SPICE that a SET logic circuit, a four-way exclusive OR, operates perfectly. It is concluded that the proposed SET logic is consistent in voltage levels and is realistic for the hybrid circuits of SETs and CMOS.

AB - A new design scheme for logic circuits utilizing single electron transistors (SETs) is proposed. First, logic operations are implemented in logic trees composed of SETs used as pull-down devices. Second, the supply voltage to SET logic trees is lower than the gate voltage swing of SETs. Third, a clock control concept similar to that of complementary metal-oxide-semiconductor (CMOS) dynamic logic is utilized. Finally, the output voltages of logic trees are amplified to the same voltage as the gate voltage swing of SETs by the CMOS inverters in order to drive the next gates. It is confirmed by the hybrid simulator of single electron tunneling and SPICE that a SET logic circuit, a four-way exclusive OR, operates perfectly. It is concluded that the proposed SET logic is consistent in voltage levels and is realistic for the hybrid circuits of SETs and CMOS.

KW - CMOS

KW - Coulomb blockade

KW - Dynamic logic circuits

KW - MOSFET

KW - SET

KW - Single electron tunneling

UR - http://www.scopus.com/inward/record.url?scp=0033309552&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033309552&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0033309552

VL - 38

SP - 4027

EP - 4032

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

SN - 0021-4922

IS - 7 B

ER -