A new design scheme for logic circuits with single electron transistors

Ken Uchida, Kazuya Matsuzawa, Akira Toriumi

Research output: Contribution to journalArticle

38 Citations (Scopus)

Abstract

A new design scheme for logic circuits utilizing single electron transistors (SETs) is proposed. First, logic operations are implemented in logic trees composed of SETs used as pull-down devices. Second, the supply voltage to SET logic trees is lower than the gate voltage swing of SETs. Third, a clock control concept similar to that of complementary metal-oxide-semiconductor (CMOS) dynamic logic is utilized. Finally, the output voltages of logic trees are amplified to the same voltage as the gate voltage swing of SETs by the CMOS inverters in order to drive the next gates. It is confirmed by the hybrid simulator of single electron tunneling and SPICE that a SET logic circuit, a four-way exclusive OR, operates perfectly. It is concluded that the proposed SET logic is consistent in voltage levels and is realistic for the hybrid circuits of SETs and CMOS.

Original languageEnglish
Pages (from-to)4027-4032
Number of pages6
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume38
Issue number7 B
Publication statusPublished - 1999 Jul 15
Externally publishedYes

Fingerprint

Single electron transistors
logic circuits
single electron transistors
Logic circuits
transistor logic
logic
Electric potential
electric potential
CMOS
Metals
hybrid circuits
transistor circuits
Gates (transistor)
inverters
Electron tunneling
SPICE
electron tunneling
clocks
simulators
Clocks

Keywords

  • CMOS
  • Coulomb blockade
  • Dynamic logic circuits
  • MOSFET
  • SET
  • Single electron tunneling

ASJC Scopus subject areas

  • Physics and Astronomy (miscellaneous)

Cite this

A new design scheme for logic circuits with single electron transistors. / Uchida, Ken; Matsuzawa, Kazuya; Toriumi, Akira.

In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol. 38, No. 7 B, 15.07.1999, p. 4027-4032.

Research output: Contribution to journalArticle

@article{3e972963313d4eb48ab422352acf3158,
title = "A new design scheme for logic circuits with single electron transistors",
abstract = "A new design scheme for logic circuits utilizing single electron transistors (SETs) is proposed. First, logic operations are implemented in logic trees composed of SETs used as pull-down devices. Second, the supply voltage to SET logic trees is lower than the gate voltage swing of SETs. Third, a clock control concept similar to that of complementary metal-oxide-semiconductor (CMOS) dynamic logic is utilized. Finally, the output voltages of logic trees are amplified to the same voltage as the gate voltage swing of SETs by the CMOS inverters in order to drive the next gates. It is confirmed by the hybrid simulator of single electron tunneling and SPICE that a SET logic circuit, a four-way exclusive OR, operates perfectly. It is concluded that the proposed SET logic is consistent in voltage levels and is realistic for the hybrid circuits of SETs and CMOS.",
keywords = "CMOS, Coulomb blockade, Dynamic logic circuits, MOSFET, SET, Single electron tunneling",
author = "Ken Uchida and Kazuya Matsuzawa and Akira Toriumi",
year = "1999",
month = "7",
day = "15",
language = "English",
volume = "38",
pages = "4027--4032",
journal = "Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes",
issn = "0021-4922",
publisher = "Japan Society of Applied Physics",
number = "7 B",

}

TY - JOUR

T1 - A new design scheme for logic circuits with single electron transistors

AU - Uchida, Ken

AU - Matsuzawa, Kazuya

AU - Toriumi, Akira

PY - 1999/7/15

Y1 - 1999/7/15

N2 - A new design scheme for logic circuits utilizing single electron transistors (SETs) is proposed. First, logic operations are implemented in logic trees composed of SETs used as pull-down devices. Second, the supply voltage to SET logic trees is lower than the gate voltage swing of SETs. Third, a clock control concept similar to that of complementary metal-oxide-semiconductor (CMOS) dynamic logic is utilized. Finally, the output voltages of logic trees are amplified to the same voltage as the gate voltage swing of SETs by the CMOS inverters in order to drive the next gates. It is confirmed by the hybrid simulator of single electron tunneling and SPICE that a SET logic circuit, a four-way exclusive OR, operates perfectly. It is concluded that the proposed SET logic is consistent in voltage levels and is realistic for the hybrid circuits of SETs and CMOS.

AB - A new design scheme for logic circuits utilizing single electron transistors (SETs) is proposed. First, logic operations are implemented in logic trees composed of SETs used as pull-down devices. Second, the supply voltage to SET logic trees is lower than the gate voltage swing of SETs. Third, a clock control concept similar to that of complementary metal-oxide-semiconductor (CMOS) dynamic logic is utilized. Finally, the output voltages of logic trees are amplified to the same voltage as the gate voltage swing of SETs by the CMOS inverters in order to drive the next gates. It is confirmed by the hybrid simulator of single electron tunneling and SPICE that a SET logic circuit, a four-way exclusive OR, operates perfectly. It is concluded that the proposed SET logic is consistent in voltage levels and is realistic for the hybrid circuits of SETs and CMOS.

KW - CMOS

KW - Coulomb blockade

KW - Dynamic logic circuits

KW - MOSFET

KW - SET

KW - Single electron tunneling

UR - http://www.scopus.com/inward/record.url?scp=0033309552&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033309552&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0033309552

VL - 38

SP - 4027

EP - 4032

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

SN - 0021-4922

IS - 7 B

ER -