A new memory module for COTS-based personal supercomputing

Noboru Tanabe, Masasige Nakatake, Hirotaka Hakozaki, Yasunori Dohi, Hironori Nakajo, Hideharu Amano

Research output: Contribution to conferencePaper

11 Citations (Scopus)

Abstract

This paper presents how to make inexpensive personal supercomputers getting the merit of commercial-off-the-shelf (COTS) continuously after the death of vector supercomputer venders. It is designed to realize this goal without any modification on CPU, bridge chips on motherboard and memory chips. Only plugging a new memory module with vector load/store function make an inexpensive home-use personal computer into a node similar to Earth simulator's one. These nodes can be connected by COTS Infiniband 4X type or 12X type switches in order to make parallel systems. COTS SO-DIMMs on the memory modules can be accessed fastly by remote nodes by using AOTF, BOTF, RDMA and remote vector load/store operations. Applications with unit striding or indexed accesses are going to be accelerated. How to accelerate NAS CG class B is shown as an example. Used evaluation methodlogy is about 500 times faster than that of SimpleScalar based methodlogy. It is predicted with bandwidth analysis that up to 8.75 times improvement can be achieved by proposed system for a single CPU Pentium4 PC without parallel processing.

Original languageEnglish
Pages40-48
Number of pages9
DOIs
Publication statusPublished - 2004 Dec 1
EventProceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2004 - Maui, HI, United States
Duration: 2004 Jan 122004 Jan 14

Other

OtherProceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2004
CountryUnited States
CityMaui, HI
Period04/1/1204/1/14

ASJC Scopus subject areas

  • Computer Science(all)

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  • Cite this

    Tanabe, N., Nakatake, M., Hakozaki, H., Dohi, Y., Nakajo, H., & Amano, H. (2004). A new memory module for COTS-based personal supercomputing. 40-48. Paper presented at Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2004, Maui, HI, United States. https://doi.org/10.1109/IWIA.2004.10019