A new memory module for memory intensive applications

Noboru Tanabe; Hirotaka Hakozaki; Masasige Nakatake; Yasunori Dohi; Hironori Nakajo; Hideharu Amano

A new memory module for memory intensive applications

Noboru Tanabe, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hironori Nakajo, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Some applications with gather / scatter operations are difficult to accelerate. These operations cause inefficient cache use in each processor and fine grain global communications in parallel systems. There are several applications with such characteristics particularly in electrical engineering. For examples, circuit simulation and power flow simulation with LU decomposition for random sparse matrix has such characteristics. This paper presents how to make inexpensive personal supercomputers to solve these problems. In order to get the merit of commercial-off-the-shelf (COTS) continuously after the death of vector supercomputer vendors, it is designed without any modification on CPU, bridge chips on motherboard and memory chips. Only plugging a new memory module with vector load / store function and communication functions make an inexpensive home-use personal computer into a node similar to Earth simulator's one. Applications with unit striding or indexed accesses are going to be accelerated. How to accelerate NAS CG is shown as an example.

Original language	English
Title of host publication	International Conference on Parallel Computing in Electrical Engineering
Subtitle of host publication	Workshop on System Design Automation, SDA, PARELEC 2004
Pages	123-128
Number of pages	6
Publication status	Published - 2004 Dec 1
Event	International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004 - Dresden, Germany Duration: 2004 Sep 7 → 2004 Sep 10

Publication series

Name	International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004

Other

Other	International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004
Country	Germany
City	Dresden
Period	04/9/7 → 04/9/10

ASJC Scopus subject areas

Engineering(all)

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Cite this

Tanabe, N., Hakozaki, H., Nakatake, M., Dohi, Y., Nakajo, H., & Amano, H. (2004). A new memory module for memory intensive applications. In International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004 (pp. 123-128). (International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004).

A new memory module for memory intensive applications. / Tanabe, Noboru; Hakozaki, Hirotaka; Nakatake, Masasige; Dohi, Yasunori; Nakajo, Hironori; Amano, Hideharu.

International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004. 2004. p. 123-128 (International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Tanabe, N, Hakozaki, H, Nakatake, M, Dohi, Y, Nakajo, H & Amano, H 2004, A new memory module for memory intensive applications. in International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004. International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004, pp. 123-128, International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004, Dresden, Germany, 04/9/7.

Tanabe N, Hakozaki H, Nakatake M, Dohi Y, Nakajo H, Amano H. A new memory module for memory intensive applications. In International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004. 2004. p. 123-128. (International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004).

Tanabe, Noboru ; Hakozaki, Hirotaka ; Nakatake, Masasige ; Dohi, Yasunori ; Nakajo, Hironori ; Amano, Hideharu. / A new memory module for memory intensive applications. International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004. 2004. pp. 123-128 (International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004).

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