A new memory module for memory intensive applications

Noboru Tanabe, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hironori Nakajo, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Some applications with gather / scatter operations are difficult to accelerate. These operations cause inefficient cache use in each processor and fine grain global communications in parallel systems. There are several applications with such characteristics particularly in electrical engineering. For examples, circuit simulation and power flow simulation with LU decomposition for random sparse matrix has such characteristics. This paper presents how to make inexpensive personal supercomputers to solve these problems. In order to get the merit of commercial-off-the-shelf (COTS) continuously after the death of vector supercomputer vendors, it is designed without any modification on CPU, bridge chips on motherboard and memory chips. Only plugging a new memory module with vector load / store function and communication functions make an inexpensive home-use personal computer into a node similar to Earth simulator's one. Applications with unit striding or indexed accesses are going to be accelerated. How to accelerate NAS CG is shown as an example.

Original languageEnglish
Title of host publicationInternational Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004
Pages123-128
Number of pages6
Publication statusPublished - 2004
EventInternational Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004 - Dresden, Germany
Duration: 2004 Sep 72004 Sep 10

Other

OtherInternational Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004
CountryGermany
CityDresden
Period04/9/704/9/10

Fingerprint

Supercomputers
Data storage equipment
Circuit simulation
Communication
Electrical engineering
Flow simulation
Personal computers
Program processors
Simulators
Earth (planet)
Decomposition

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Tanabe, N., Hakozaki, H., Nakatake, M., Dohi, Y., Nakajo, H., & Amano, H. (2004). A new memory module for memory intensive applications. In International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004 (pp. 123-128)

A new memory module for memory intensive applications. / Tanabe, Noboru; Hakozaki, Hirotaka; Nakatake, Masasige; Dohi, Yasunori; Nakajo, Hironori; Amano, Hideharu.

International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004. 2004. p. 123-128.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tanabe, N, Hakozaki, H, Nakatake, M, Dohi, Y, Nakajo, H & Amano, H 2004, A new memory module for memory intensive applications. in International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004. pp. 123-128, International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004, Dresden, Germany, 04/9/7.
Tanabe N, Hakozaki H, Nakatake M, Dohi Y, Nakajo H, Amano H. A new memory module for memory intensive applications. In International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004. 2004. p. 123-128
Tanabe, Noboru ; Hakozaki, Hirotaka ; Nakatake, Masasige ; Dohi, Yasunori ; Nakajo, Hironori ; Amano, Hideharu. / A new memory module for memory intensive applications. International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004. 2004. pp. 123-128
@inproceedings{f08e157dcda4470bbd752eb5a9110001,
title = "A new memory module for memory intensive applications",
abstract = "Some applications with gather / scatter operations are difficult to accelerate. These operations cause inefficient cache use in each processor and fine grain global communications in parallel systems. There are several applications with such characteristics particularly in electrical engineering. For examples, circuit simulation and power flow simulation with LU decomposition for random sparse matrix has such characteristics. This paper presents how to make inexpensive personal supercomputers to solve these problems. In order to get the merit of commercial-off-the-shelf (COTS) continuously after the death of vector supercomputer vendors, it is designed without any modification on CPU, bridge chips on motherboard and memory chips. Only plugging a new memory module with vector load / store function and communication functions make an inexpensive home-use personal computer into a node similar to Earth simulator's one. Applications with unit striding or indexed accesses are going to be accelerated. How to accelerate NAS CG is shown as an example.",
author = "Noboru Tanabe and Hirotaka Hakozaki and Masasige Nakatake and Yasunori Dohi and Hironori Nakajo and Hideharu Amano",
year = "2004",
language = "English",
isbn = "0769520804",
pages = "123--128",
booktitle = "International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004",

}

TY - GEN

T1 - A new memory module for memory intensive applications

AU - Tanabe, Noboru

AU - Hakozaki, Hirotaka

AU - Nakatake, Masasige

AU - Dohi, Yasunori

AU - Nakajo, Hironori

AU - Amano, Hideharu

PY - 2004

Y1 - 2004

N2 - Some applications with gather / scatter operations are difficult to accelerate. These operations cause inefficient cache use in each processor and fine grain global communications in parallel systems. There are several applications with such characteristics particularly in electrical engineering. For examples, circuit simulation and power flow simulation with LU decomposition for random sparse matrix has such characteristics. This paper presents how to make inexpensive personal supercomputers to solve these problems. In order to get the merit of commercial-off-the-shelf (COTS) continuously after the death of vector supercomputer vendors, it is designed without any modification on CPU, bridge chips on motherboard and memory chips. Only plugging a new memory module with vector load / store function and communication functions make an inexpensive home-use personal computer into a node similar to Earth simulator's one. Applications with unit striding or indexed accesses are going to be accelerated. How to accelerate NAS CG is shown as an example.

AB - Some applications with gather / scatter operations are difficult to accelerate. These operations cause inefficient cache use in each processor and fine grain global communications in parallel systems. There are several applications with such characteristics particularly in electrical engineering. For examples, circuit simulation and power flow simulation with LU decomposition for random sparse matrix has such characteristics. This paper presents how to make inexpensive personal supercomputers to solve these problems. In order to get the merit of commercial-off-the-shelf (COTS) continuously after the death of vector supercomputer vendors, it is designed without any modification on CPU, bridge chips on motherboard and memory chips. Only plugging a new memory module with vector load / store function and communication functions make an inexpensive home-use personal computer into a node similar to Earth simulator's one. Applications with unit striding or indexed accesses are going to be accelerated. How to accelerate NAS CG is shown as an example.

UR - http://www.scopus.com/inward/record.url?scp=13944277269&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=13944277269&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:13944277269

SN - 0769520804

SN - 9780769520803

SP - 123

EP - 128

BT - International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004

ER -