A Novel Concept for High-Speed Time Switch Approaching Memory Read Cycle Limit

Yousuke Yamamoto, Hiroshi Miyanaga, Yoshiji Kobayashi, Yasukazu Terada, Naoaki Yamanaka

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

A novel concept and structure for a high-speed time division switch operating in the gigabit/second range are presented. The basic concept is to use the high-speed memory in the time switch effectively by means of a slow writing/fast reading method. N numbers of speech data are written in parallel during N clock times and read serially during one clock time for one switched datum. By using the concept and high-speed memories that we have, a data switching system which approaches the memory and read cycle limit can be realized with a proper time margin.

Original languageEnglish
Pages (from-to)953-955
Number of pages3
JournalIEEE Transactions on Communications
Volume34
Issue number9
DOIs
Publication statusPublished - 1986
Externally publishedYes

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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