This paper presents a parallel algorithm for timeslot assignment problems in TDM hierarchical switching systems, based on the neural network model. The TDM systems are operated. in repetitive frames composed of several Time-Slots. A Time-Slot represents a switching configuration where one packet is transmitted through an I/O line. The goal of our algorithm is to find conflict-free Time-Slot assignments for given switching demands. The algorithm runs on a maximum of n2×m processors for m-Time-Slot problems in n×n TDM systems. In small problems up to a 24×24 TDM system, the algorithm can find the optimum solution in a nearly constant time, when it is performed on n2×m processors.
ASJC Scopus subject areas
- Electrical and Electronic Engineering