A parallel multi-layer channel router on the HVH model

Nobuo Funabaki, Yoshiyasu Takefuji

Research output: Contribution to journalArticle

Abstract

With the advancement of the silicon technology multi-layered VLSI circuits and PCBs (printed circuit boards) have been widely used. Based on the neural network model this paper presents the first parallel algorithm for multi-layer channel routing problems on the HVH model which minimize wiring areas in VLSI circuits and PCBs. The algorithm requires n × m × 2s processing elements for the n-net-m-track-3s-layer problem. The algorithm not only runs on a sequential machine but also on a parallel machine with maximally n × m × 2s processors. The algorithm is verified by solving seven benchmark problems where it finds better solutions than the existing algorithms for 6-12-layer problems in nearly constant time on a parallel machine.

Original languageEnglish
Pages (from-to)63-77
Number of pages15
JournalParallel Computing
Volume19
Issue number1
DOIs
Publication statusPublished - 1993

Fingerprint

Router
Routers
Multilayer
VLSI Circuits
Printed Circuit Board
VLSI circuits
Parallel Machines
Printed circuit boards
Channel Routing
Sequential machines
Routing Problem
Electric wiring
Time Constant
Parallel algorithms
Neural Network Model
Model
Parallel Algorithms
Silicon
Benchmark
Neural networks

Keywords

  • benchmark problems
  • Channel routing problems
  • HVH model
  • neural network
  • simulation results
  • VLSI circuits

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

A parallel multi-layer channel router on the HVH model. / Funabaki, Nobuo; Takefuji, Yoshiyasu.

In: Parallel Computing, Vol. 19, No. 1, 1993, p. 63-77.

Research output: Contribution to journalArticle

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