A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V

Isamu Hayashi; Takeshi Matsubara; Satoshi Kumaki; Abul Hasan Johari; Hiroki Ishikuro; Tadahiro Kuroda

doi:10.1109/ASSCC.2010.5716596

A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V

Isamu Hayashi, Takeshi Matsubara, Satoshi Kumaki, Abul Hasan Johari, Hiroki Ishikuro, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

A Phase-to-Digital Converter (PDC), - an improved scheme of Time-to-Digital Converter (TDC) -, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL).

Original language	English
Title of host publication	2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Pages	225-228
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2010.5716596
Publication status	Published - 2010 Dec 1
Event	2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 - Beijing, China Duration: 2010 Nov 8 → 2010 Nov 10

Publication series

Name	2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Other

Other	2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Country/Territory	China
City	Beijing
Period	10/11/8 → 10/11/10

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASSCC.2010.5716596

Cite this

Hayashi, I., Matsubara, T., Kumaki, S., Johari, A. H., Ishikuro, H., & Kuroda, T. (2010). A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V. In 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 (pp. 225-228). [5716596] (2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010). https://doi.org/10.1109/ASSCC.2010.5716596

A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V. / Hayashi, Isamu; Matsubara, Takeshi; Kumaki, Satoshi et al.

2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010. 2010. p. 225-228 5716596 (2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hayashi, I, Matsubara, T, Kumaki, S, Johari, AH, Ishikuro, H & Kuroda, T 2010, A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V. in 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010., 5716596, 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, pp. 225-228, 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, Beijing, China, 10/11/8. https://doi.org/10.1109/ASSCC.2010.5716596

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abstract = "A Phase-to-Digital Converter (PDC), - an improved scheme of Time-to-Digital Converter (TDC) -, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL).",

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AU - Ishikuro, Hiroki

AU - Kuroda, Tadahiro

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N2 - A Phase-to-Digital Converter (PDC), - an improved scheme of Time-to-Digital Converter (TDC) -, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL).

AB - A Phase-to-Digital Converter (PDC), - an improved scheme of Time-to-Digital Converter (TDC) -, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL).

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A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V

Abstract

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