A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V

Isamu Hayashi, Takeshi Matsubara, Satoshi Kumaki, Abul Hasan Johari, Hiroki Ishikuro, Tadahiro Kuroda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)

    Abstract

    A Phase-to-Digital Converter (PDC), - an improved scheme of Time-to-Digital Converter (TDC) -, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL).

    Original languageEnglish
    Title of host publication2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
    Pages225-228
    Number of pages4
    DOIs
    Publication statusPublished - 2010 Dec 1
    Event2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 - Beijing, China
    Duration: 2010 Nov 82010 Nov 10

    Publication series

    Name2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

    Other

    Other2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
    CountryChina
    CityBeijing
    Period10/11/810/11/10

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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