A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V

Isamu Hayashi, Takeshi Matsubara, Satoshi Kumaki, Abul Hasan Johari, Hiroki Ishikuro, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A Phase-to-Digital Converter (PDC), - an improved scheme of Time-to-Digital Converter (TDC) -, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL).

Original languageEnglish
Title of host publication2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Pages225-228
Number of pages4
DOIs
Publication statusPublished - 2010
Event2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 - Beijing, China
Duration: 2010 Nov 82010 Nov 10

Other

Other2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
CountryChina
CityBeijing
Period10/11/810/11/10

Fingerprint

Phase locked loops
Clocks
Tuning
Calibration

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Hayashi, I., Matsubara, T., Kumaki, S., Johari, A. H., Ishikuro, H., & Kuroda, T. (2010). A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V. In 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 (pp. 225-228). [5716596] https://doi.org/10.1109/ASSCC.2010.5716596

A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V. / Hayashi, Isamu; Matsubara, Takeshi; Kumaki, Satoshi; Johari, Abul Hasan; Ishikuro, Hiroki; Kuroda, Tadahiro.

2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010. 2010. p. 225-228 5716596.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hayashi, I, Matsubara, T, Kumaki, S, Johari, AH, Ishikuro, H & Kuroda, T 2010, A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V. in 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010., 5716596, pp. 225-228, 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, Beijing, China, 10/11/8. https://doi.org/10.1109/ASSCC.2010.5716596
Hayashi I, Matsubara T, Kumaki S, Johari AH, Ishikuro H, Kuroda T. A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V. In 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010. 2010. p. 225-228. 5716596 https://doi.org/10.1109/ASSCC.2010.5716596
Hayashi, Isamu ; Matsubara, Takeshi ; Kumaki, Satoshi ; Johari, Abul Hasan ; Ishikuro, Hiroki ; Kuroda, Tadahiro. / A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V. 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010. 2010. pp. 225-228
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