A port combination methodology for application-specific networks-on-chip on FPGAS

Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Research output: Contribution to journalArticle

Abstract

A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize required hardware amount. Given the traffic characteristics of the target application and the expected hardware amount reduction rate, the algorithm automatically makes the port combination plan for the networks. Since the port combination technique has the advantage of almost keeping the topology including twosurface layout, it does not affect the design of the other layer, such as task mapping and scheduling. The algorithm shows much better efficiency than the algorithm without temporal correlation. For the multimedia stream processing application, the algorithm can save 55% of the hardware amount without performance degradation, while the none temporal correlation algorithm suffers from 30% performance loss.

Original languageEnglish
Pages (from-to)1914-1922
Number of pages9
JournalIEICE Transactions on Information and Systems
VolumeE90-D
Issue number12
DOIs
Publication statusPublished - 2007 Dec

Fingerprint

Hardware
Routers
Network-on-chip
Scheduling
Topology
Degradation
Processing

Keywords

  • Fpga
  • Networks-on-chip
  • Port combination
  • Router

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Software
  • Artificial Intelligence
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition

Cite this

A port combination methodology for application-specific networks-on-chip on FPGAS. / Wang, Daihan; Matsutani, Hiroki; Koibuchi, Michihiro; Amano, Hideharu.

In: IEICE Transactions on Information and Systems, Vol. E90-D, No. 12, 12.2007, p. 1914-1922.

Research output: Contribution to journalArticle

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