A power scalable SAR-ADC in 0.18μm-CMOS with 0.5V nano-watt operation

Ryota Sekimoto, Akira Shikata, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

This paper presents an extremely low-power and low-voltage Analog-to-Digital Converter (ADC) for wireless sensor networks or medical implantable devices. Top plate sampling and bootstrap switch are used to realize ultra low-voltage (0.5V) operation. Configuration of capacitor array which can decrease the number of control bus lines are proposed to reduce the circuit area and power consumption. To further reduce the power consumption, optimal power supply voltages are determined independently for analog blocks and digital blocks considering the tradeoff between the speed and power. Test ADC chip fabricated in 0.18μm-CMOS process has achieved 0.5V, 6nW operation at sampling frequency of 0.4kS/s. The achieved effective number of bit (ENOB) is 7.19-bit. When the supply voltage is increased to 1V, the ADC operates at 820kS/s with power consumption of 30.9μW and ENOB of 7.41-bit.

Original languageEnglish
Title of host publicationProceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011
Pages89-94
Number of pages6
DOIs
Publication statusPublished - 2011
Event2011 1st International Symposium on Access Spaces, ISAS 2011 - Yokohama, Japan
Duration: 2011 Jun 172011 Jun 19

Other

Other2011 1st International Symposium on Access Spaces, ISAS 2011
CountryJapan
CityYokohama
Period11/6/1711/6/19

Fingerprint

Digital to analog conversion
Electric power utilization
Electric potential
Sampling
Wireless sensor networks
Capacitors
Switches
Networks (circuits)

Keywords

  • bootstrap switch
  • low-power
  • low-voltage
  • medical implantable
  • sensor network
  • successive-approximation-register(SAR) ADC
  • top plate sampling

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Sekimoto, R., Shikata, A., & Ishikuro, H. (2011). A power scalable SAR-ADC in 0.18μm-CMOS with 0.5V nano-watt operation. In Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011 (pp. 89-94). [5960926] https://doi.org/10.1109/ISAS.2011.5960926

A power scalable SAR-ADC in 0.18μm-CMOS with 0.5V nano-watt operation. / Sekimoto, Ryota; Shikata, Akira; Ishikuro, Hiroki.

Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011. 2011. p. 89-94 5960926.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sekimoto, R, Shikata, A & Ishikuro, H 2011, A power scalable SAR-ADC in 0.18μm-CMOS with 0.5V nano-watt operation. in Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011., 5960926, pp. 89-94, 2011 1st International Symposium on Access Spaces, ISAS 2011, Yokohama, Japan, 11/6/17. https://doi.org/10.1109/ISAS.2011.5960926
Sekimoto R, Shikata A, Ishikuro H. A power scalable SAR-ADC in 0.18μm-CMOS with 0.5V nano-watt operation. In Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011. 2011. p. 89-94. 5960926 https://doi.org/10.1109/ISAS.2011.5960926
Sekimoto, Ryota ; Shikata, Akira ; Ishikuro, Hiroki. / A power scalable SAR-ADC in 0.18μm-CMOS with 0.5V nano-watt operation. Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011. 2011. pp. 89-94
@inproceedings{503ff7ace1c44a7798280dbaeaf3e9a5,
title = "A power scalable SAR-ADC in 0.18μm-CMOS with 0.5V nano-watt operation",
abstract = "This paper presents an extremely low-power and low-voltage Analog-to-Digital Converter (ADC) for wireless sensor networks or medical implantable devices. Top plate sampling and bootstrap switch are used to realize ultra low-voltage (0.5V) operation. Configuration of capacitor array which can decrease the number of control bus lines are proposed to reduce the circuit area and power consumption. To further reduce the power consumption, optimal power supply voltages are determined independently for analog blocks and digital blocks considering the tradeoff between the speed and power. Test ADC chip fabricated in 0.18μm-CMOS process has achieved 0.5V, 6nW operation at sampling frequency of 0.4kS/s. The achieved effective number of bit (ENOB) is 7.19-bit. When the supply voltage is increased to 1V, the ADC operates at 820kS/s with power consumption of 30.9μW and ENOB of 7.41-bit.",
keywords = "bootstrap switch, low-power, low-voltage, medical implantable, sensor network, successive-approximation-register(SAR) ADC, top plate sampling",
author = "Ryota Sekimoto and Akira Shikata and Hiroki Ishikuro",
year = "2011",
doi = "10.1109/ISAS.2011.5960926",
language = "English",
isbn = "9781457707179",
pages = "89--94",
booktitle = "Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011",

}

TY - GEN

T1 - A power scalable SAR-ADC in 0.18μm-CMOS with 0.5V nano-watt operation

AU - Sekimoto, Ryota

AU - Shikata, Akira

AU - Ishikuro, Hiroki

PY - 2011

Y1 - 2011

N2 - This paper presents an extremely low-power and low-voltage Analog-to-Digital Converter (ADC) for wireless sensor networks or medical implantable devices. Top plate sampling and bootstrap switch are used to realize ultra low-voltage (0.5V) operation. Configuration of capacitor array which can decrease the number of control bus lines are proposed to reduce the circuit area and power consumption. To further reduce the power consumption, optimal power supply voltages are determined independently for analog blocks and digital blocks considering the tradeoff between the speed and power. Test ADC chip fabricated in 0.18μm-CMOS process has achieved 0.5V, 6nW operation at sampling frequency of 0.4kS/s. The achieved effective number of bit (ENOB) is 7.19-bit. When the supply voltage is increased to 1V, the ADC operates at 820kS/s with power consumption of 30.9μW and ENOB of 7.41-bit.

AB - This paper presents an extremely low-power and low-voltage Analog-to-Digital Converter (ADC) for wireless sensor networks or medical implantable devices. Top plate sampling and bootstrap switch are used to realize ultra low-voltage (0.5V) operation. Configuration of capacitor array which can decrease the number of control bus lines are proposed to reduce the circuit area and power consumption. To further reduce the power consumption, optimal power supply voltages are determined independently for analog blocks and digital blocks considering the tradeoff between the speed and power. Test ADC chip fabricated in 0.18μm-CMOS process has achieved 0.5V, 6nW operation at sampling frequency of 0.4kS/s. The achieved effective number of bit (ENOB) is 7.19-bit. When the supply voltage is increased to 1V, the ADC operates at 820kS/s with power consumption of 30.9μW and ENOB of 7.41-bit.

KW - bootstrap switch

KW - low-power

KW - low-voltage

KW - medical implantable

KW - sensor network

KW - successive-approximation-register(SAR) ADC

KW - top plate sampling

UR - http://www.scopus.com/inward/record.url?scp=80051811500&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80051811500&partnerID=8YFLogxK

U2 - 10.1109/ISAS.2011.5960926

DO - 10.1109/ISAS.2011.5960926

M3 - Conference contribution

SN - 9781457707179

SP - 89

EP - 94

BT - Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011

ER -