TY - GEN
T1 - A Preliminary evaluation of building block computing systems
AU - Terashima, Sayaka
AU - Kojima, Takuya
AU - Okuhara, Hayate
AU - Musha, Kazusa
AU - Amano, Hideharu
AU - Sakamoto, Ryuichi
AU - Kondo, Masaaki
AU - Namiki, Mitaro
N1 - Funding Information:
This work is partially supported by JSPS KAKENHI S Grant Number 25220002 and JSPS KAKENHI B Grant Number 18H03215. This work is supported by VLSI Design and Education Center(VDEC), the University of Tokyo in collaboration with Synopsys, Inc and Cadence Design Systems, Inc.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/10
Y1 - 2019/10
N2 - A building block computing system with inductive coupling Through Chip Interface (TCI) consists of 3-D chip stack, each of which is small dedicated chips. By changing the combination of stacked chips, various types of systems can be built. A MIPS R3000 compatible processor GeyserTT, a neural network accelerator SNACC and the shared memory for building the twin-Tower of chips SMTT have been developed with a Renesas 65nm low leakage CMOS process. They provide the TCI IP (Intellectual Property), and an escalator network is built just by stacking them. This paper shows each chip evaluation results and performance estimation of stacking them with the RTL simulator. The performance of the single-Tower and twin-Tower configuration is estimated by RTL simulation when a part of Alexnet is implemented. The evaluation results showed that the single-Tower configuration with GeyserTT+SNACC achieved about twice performance as the case with GeyserTT. Also, experimental results using each of the single real chip showed that all of them work at least 50MHz with extremely low power consumption. The twin-Tower configuration achieved about 2x of the single-Tower, that is about 6x of GeyserTT. The power consumption was about 276mW for the single-Tower and 496mW for the twin-Tower.
AB - A building block computing system with inductive coupling Through Chip Interface (TCI) consists of 3-D chip stack, each of which is small dedicated chips. By changing the combination of stacked chips, various types of systems can be built. A MIPS R3000 compatible processor GeyserTT, a neural network accelerator SNACC and the shared memory for building the twin-Tower of chips SMTT have been developed with a Renesas 65nm low leakage CMOS process. They provide the TCI IP (Intellectual Property), and an escalator network is built just by stacking them. This paper shows each chip evaluation results and performance estimation of stacking them with the RTL simulator. The performance of the single-Tower and twin-Tower configuration is estimated by RTL simulation when a part of Alexnet is implemented. The evaluation results showed that the single-Tower configuration with GeyserTT+SNACC achieved about twice performance as the case with GeyserTT. Also, experimental results using each of the single real chip showed that all of them work at least 50MHz with extremely low power consumption. The twin-Tower configuration achieved about 2x of the single-Tower, that is about 6x of GeyserTT. The power consumption was about 276mW for the single-Tower and 496mW for the twin-Tower.
KW - 3D chip stacking
KW - CNN
KW - Efficient accelerator
KW - TCI
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U2 - 10.1109/MCSoC.2019.00051
DO - 10.1109/MCSoC.2019.00051
M3 - Conference contribution
AN - SCOPUS:85076159222
T3 - Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019
SP - 312
EP - 319
BT - Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 13th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019
Y2 - 1 October 2019 through 4 October 2019
ER -