A Preliminary evaluation of building block computing systems

Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Kazusa Musha, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Mitaro Namiki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A building block computing system with inductive coupling Through Chip Interface (TCI) consists of 3-D chip stack, each of which is small dedicated chips. By changing the combination of stacked chips, various types of systems can be built. A MIPS R3000 compatible processor GeyserTT, a neural network accelerator SNACC and the shared memory for building the twin-Tower of chips SMTT have been developed with a Renesas 65nm low leakage CMOS process. They provide the TCI IP (Intellectual Property), and an escalator network is built just by stacking them. This paper shows each chip evaluation results and performance estimation of stacking them with the RTL simulator. The performance of the single-Tower and twin-Tower configuration is estimated by RTL simulation when a part of Alexnet is implemented. The evaluation results showed that the single-Tower configuration with GeyserTT+SNACC achieved about twice performance as the case with GeyserTT. Also, experimental results using each of the single real chip showed that all of them work at least 50MHz with extremely low power consumption. The twin-Tower configuration achieved about 2x of the single-Tower, that is about 6x of GeyserTT. The power consumption was about 276mW for the single-Tower and 496mW for the twin-Tower.

Original languageEnglish
Title of host publicationProceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages312-319
Number of pages8
ISBN (Electronic)9781728148823
DOIs
Publication statusPublished - 2019 Oct
Event13th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019 - Singapore, Singapore
Duration: 2019 Oct 12019 Oct 4

Publication series

NameProceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019

Conference

Conference13th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019
CountrySingapore
CitySingapore
Period19/10/119/10/4

Fingerprint

Building Blocks
Towers
Chip
Computing
Evaluation
Stacking
Configuration
Power Consumption
Electric power utilization
Escalators
Intellectual Property
Intellectual property
Shared Memory
Accelerator
Leakage
3D
Particle accelerators
Simulator
Simulators
Neural Networks

Keywords

  • 3D chip stacking
  • CNN
  • Efficient accelerator
  • TCI

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Control and Optimization

Cite this

Terashima, S., Kojima, T., Okuhara, H., Musha, K., Amano, H., Sakamoto, R., ... Namiki, M. (2019). A Preliminary evaluation of building block computing systems. In Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019 (pp. 312-319). [8906777] (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MCSoC.2019.00051

A Preliminary evaluation of building block computing systems. / Terashima, Sayaka; Kojima, Takuya; Okuhara, Hayate; Musha, Kazusa; Amano, Hideharu; Sakamoto, Ryuichi; Kondo, Masaaki; Namiki, Mitaro.

Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 312-319 8906777 (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Terashima, S, Kojima, T, Okuhara, H, Musha, K, Amano, H, Sakamoto, R, Kondo, M & Namiki, M 2019, A Preliminary evaluation of building block computing systems. in Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019., 8906777, Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019, Institute of Electrical and Electronics Engineers Inc., pp. 312-319, 13th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019, Singapore, Singapore, 19/10/1. https://doi.org/10.1109/MCSoC.2019.00051
Terashima S, Kojima T, Okuhara H, Musha K, Amano H, Sakamoto R et al. A Preliminary evaluation of building block computing systems. In Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 312-319. 8906777. (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019). https://doi.org/10.1109/MCSoC.2019.00051
Terashima, Sayaka ; Kojima, Takuya ; Okuhara, Hayate ; Musha, Kazusa ; Amano, Hideharu ; Sakamoto, Ryuichi ; Kondo, Masaaki ; Namiki, Mitaro. / A Preliminary evaluation of building block computing systems. Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 312-319 (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).
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