A Programmable δΣSAR-ADC with charge shuttling technique

Kohei Yamada, Yosuke Toyama, Hiroki Ishikuro

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)


    This paper presents an ADC with programmability between SAR-only mode and delta-sigma (δΣassisted mode. The ?assisted mode brings 1st order noise shaping for resolution enhancement. Proposed charge shuttling technique makes it possible to share a charge re-distribution capacitor array for DAC in SAR, feedback DAC, and integrator capacitor in δΣloop and improve the accuracy. The prototype ADC fabricated in 65- nm CMOS achieved SNDR of 44.35 dB at sampling rate of 32 MHz and power consumption of 0.55mW. The SNDR is improved to 62.9dB by δΣassisted mode when the signal bandwidth is 60 kHz.

    Original languageEnglish
    Title of host publicationISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Number of pages2
    ISBN (Electronic)9781467393089
    Publication statusPublished - 2016 Dec 27
    Event13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of
    Duration: 2016 Oct 232016 Oct 26


    Other13th International SoC Design Conference, ISOCC 2016
    Country/TerritoryKorea, Republic of


    • Charge shuttling
    • Delta-sigma
    • Programmable
    • SAR

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Instrumentation


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