A prototype of a dynamically reconfigurable processor based off-loading engine for accelerating the shortest path calculation with GNU zebra

Sho Shimizu, Taku Kihara, Yutaka Arakawa, Naoaki Yamanaka, Kosuke Shiba

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A hardware off-loading engine to speed up the shortest path calculation in OSPF (Open Shortest Path First) has been developed. The developed system is co-designed with both hardware and software to optimize an architecture of a router for highly functional Traffic Engineering (TE). To speed up the shortest path calculation, we employ a dynamically reconflgurable processor, IPFlex DAPDNA-2, as a hardware off- loader, and newly structured a novel high-speed parallel shortest path algorithm, called MPSA (Multi-route Parallel Search Algorithm). The proposed algorithm consists of simple processing, in which multiple paths are simultaneously searched by multiple Processor Element (PE) of DAPDNA-2. Therefore, it reduces the execution time of shortest path calculation to 2.8% compared with the popular shortest path algorithm, Dijkstra's algorithm. Our prototype works together with a famous software-based router, GNU Zebra, on commodity Linux PC. The proposed architecture and prototype system can be applied to future network sophisticated TE.

Original languageEnglish
Title of host publication2008 International Conference on High Performance Switching and Routing, HPSR 2008
Pages131-136
Number of pages6
DOIs
Publication statusPublished - 2008
Event2008 International Conference on High Performance Switching and Routing, HPSR 2008 - Shanghai, China
Duration: 2008 May 152008 May 17

Other

Other2008 International Conference on High Performance Switching and Routing, HPSR 2008
CountryChina
CityShanghai
Period08/5/1508/5/17

Fingerprint

Engines
Hardware
Routers
Loaders
Processing

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Shimizu, S., Kihara, T., Arakawa, Y., Yamanaka, N., & Shiba, K. (2008). A prototype of a dynamically reconfigurable processor based off-loading engine for accelerating the shortest path calculation with GNU zebra. In 2008 International Conference on High Performance Switching and Routing, HPSR 2008 (pp. 131-136). [4734433] https://doi.org/10.1109/HSPR.2008.4734433

A prototype of a dynamically reconfigurable processor based off-loading engine for accelerating the shortest path calculation with GNU zebra. / Shimizu, Sho; Kihara, Taku; Arakawa, Yutaka; Yamanaka, Naoaki; Shiba, Kosuke.

2008 International Conference on High Performance Switching and Routing, HPSR 2008. 2008. p. 131-136 4734433.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shimizu, S, Kihara, T, Arakawa, Y, Yamanaka, N & Shiba, K 2008, A prototype of a dynamically reconfigurable processor based off-loading engine for accelerating the shortest path calculation with GNU zebra. in 2008 International Conference on High Performance Switching and Routing, HPSR 2008., 4734433, pp. 131-136, 2008 International Conference on High Performance Switching and Routing, HPSR 2008, Shanghai, China, 08/5/15. https://doi.org/10.1109/HSPR.2008.4734433
Shimizu S, Kihara T, Arakawa Y, Yamanaka N, Shiba K. A prototype of a dynamically reconfigurable processor based off-loading engine for accelerating the shortest path calculation with GNU zebra. In 2008 International Conference on High Performance Switching and Routing, HPSR 2008. 2008. p. 131-136. 4734433 https://doi.org/10.1109/HSPR.2008.4734433
Shimizu, Sho ; Kihara, Taku ; Arakawa, Yutaka ; Yamanaka, Naoaki ; Shiba, Kosuke. / A prototype of a dynamically reconfigurable processor based off-loading engine for accelerating the shortest path calculation with GNU zebra. 2008 International Conference on High Performance Switching and Routing, HPSR 2008. 2008. pp. 131-136
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