A runtime optimization selection framework to realize energy efficient networks-on-chip

Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura

Research output: Contribution to journalArticlepeer-review


Networks-on-Chip (or NoCs, for short) play important roles in modern and future multi-core processors as they are highly related to both performance and power consumption of the entire chip. Up to date, many optimization techniques have been developed to improve NoC's bandwidth, latency and power consumption. But a clear answer to how energy efficiency is affected with these optimization techniques is yet to be found since each of these optimization techniques comes with its own benefits and overheads while there are also too many of them. Thus, here comes the problem of when and how such optimization techniques should be applied. In order to solve this problem, we build a runtime framework to throttle these optimization techniques based on concise performance and energy models. With the help of this framework, we can successfully establish adaptive selections over multiple optimization techniques to further improve performance or energy efficiency of the network at runtime.

Original languageEnglish
Pages (from-to)2881-2890
Number of pages10
JournalIEICE Transactions on Information and Systems
Issue number12
Publication statusPublished - 2016 Dec
Externally publishedYes


  • Energy efficiency
  • Networks-on-Chip
  • Optimization
  • Performance
  • Selection

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence


Dive into the research topics of 'A runtime optimization selection framework to realize energy efficient networks-on-chip'. Together they form a unique fingerprint.

Cite this