A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

Yoshinori Kohama; Yasufumi Sugimori; Shotaro Saito; Yohei Hasegawa; Toru Sano; Kazutaka Kasuga; Yoichi Yoshida; Kiichi Niitsu; Noriyuki Miura; Hideharu Amano; Tadahiro Kuroda

A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

Yoshinori Kohama, Yasufumi Sugimori, Shotaro Saito, Yohei Hasegawa, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Hideharu Amano, Tadahiro Kuroda

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

15 Citations (Scopus)

Abstract

This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031mm2. Average execution time is reduced to 31% compared to that using one chip.

Original language	English
Title of host publication	2009 Symposium on VLSI Circuits
Pages	94-95
Number of pages	2
Publication status	Published - 2009 Nov 18
Event	2009 Symposium on VLSI Circuits - Kyoto, Japan Duration: 2009 Jun 16 → 2009 Jun 18

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2009 Symposium on VLSI Circuits
Country	Japan
City	Kyoto
Period	09/6/16 → 09/6/18

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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Cite this

Kohama, Y., Sugimori, Y., Saito, S., Hasegawa, Y., Sano, T., Kasuga, K., Yoshida, Y., Niitsu, K., Miura, N., Amano, H., & Kuroda, T. (2009). A scalable 3D processor by homogeneous chip stacking with inductive-coupling link. In 2009 Symposium on VLSI Circuits (pp. 94-95). [5205288] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

A scalable 3D processor by homogeneous chip stacking with inductive-coupling link. / Kohama, Yoshinori; Sugimori, Yasufumi; Saito, Shotaro; Hasegawa, Yohei; Sano, Toru; Kasuga, Kazutaka; Yoshida, Yoichi; Niitsu, Kiichi; Miura, Noriyuki; Amano, Hideharu; Kuroda, Tadahiro.

2009 Symposium on VLSI Circuits. 2009. p. 94-95 5205288 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kohama, Y, Sugimori, Y, Saito, S, Hasegawa, Y, Sano, T, Kasuga, K, Yoshida, Y, Niitsu, K, Miura, N, Amano, H & Kuroda, T 2009, A scalable 3D processor by homogeneous chip stacking with inductive-coupling link. in 2009 Symposium on VLSI Circuits., 5205288, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 94-95, 2009 Symposium on VLSI Circuits, Kyoto, Japan, 09/6/16.

Kohama, Yoshinori ; Sugimori, Yasufumi ; Saito, Shotaro ; Hasegawa, Yohei ; Sano, Toru ; Kasuga, Kazutaka ; Yoshida, Yoichi ; Niitsu, Kiichi ; Miura, Noriyuki ; Amano, Hideharu ; Kuroda, Tadahiro. / A scalable 3D processor by homogeneous chip stacking with inductive-coupling link. 2009 Symposium on VLSI Circuits. 2009. pp. 94-95 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

@inproceedings{b267457fd7a940a7be554794affac6e5,

title = "A scalable 3D processor by homogeneous chip stacking with inductive-coupling link",

abstract = "This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031mm2. Average execution time is reduced to 31% compared to that using one chip.",

author = "Yoshinori Kohama and Yasufumi Sugimori and Shotaro Saito and Yohei Hasegawa and Toru Sano and Kazutaka Kasuga and Yoichi Yoshida and Kiichi Niitsu and Noriyuki Miura and Hideharu Amano and Tadahiro Kuroda",

year = "2009",

month = nov,

day = "18",

language = "English",

isbn = "9784863480018",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "94--95",

booktitle = "2009 Symposium on VLSI Circuits",

note = "2009 Symposium on VLSI Circuits ; Conference date: 16-06-2009 Through 18-06-2009",

}

TY - GEN

T1 - A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

AU - Kohama, Yoshinori

AU - Sugimori, Yasufumi

AU - Saito, Shotaro

AU - Hasegawa, Yohei

AU - Sano, Toru

AU - Kasuga, Kazutaka

AU - Yoshida, Yoichi

AU - Niitsu, Kiichi

AU - Miura, Noriyuki

AU - Amano, Hideharu

AU - Kuroda, Tadahiro

PY - 2009/11/18

Y1 - 2009/11/18

N2 - This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031mm2. Average execution time is reduced to 31% compared to that using one chip.

AB - This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031mm2. Average execution time is reduced to 31% compared to that using one chip.

UR - http://www.scopus.com/inward/record.url?scp=70449427842&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70449427842&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:70449427842

SN - 9784863480018

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 94

EP - 95

BT - 2009 Symposium on VLSI Circuits

T2 - 2009 Symposium on VLSI Circuits

Y2 - 16 June 2009 through 18 June 2009

ER -