Abstract
This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031mm2. Average execution time is reduced to 31% compared to that using one chip.
| Original language | English |
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| Title of host publication | 2009 Symposium on VLSI Circuits |
| Pages | 94-95 |
| Number of pages | 2 |
| Publication status | Published - 2009 Nov 18 |
| Event | 2009 Symposium on VLSI Circuits - Kyoto, Japan Duration: 2009 Jun 16 → 2009 Jun 18 |
Publication series
| Name | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
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Other
| Other | 2009 Symposium on VLSI Circuits |
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| Country | Japan |
| City | Kyoto |
| Period | 09/6/16 → 09/6/18 |
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ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
Kohama, Y., Sugimori, Y., Saito, S., Hasegawa, Y., Sano, T., Kasuga, K., Yoshida, Y., Niitsu, K., Miura, N., Amano, H., & Kuroda, T. (2009). A scalable 3D processor by homogeneous chip stacking with inductive-coupling link. In 2009 Symposium on VLSI Circuits (pp. 94-95). [5205288] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).