Abstract
This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031mm2. Average execution time is reduced to 31% compared to that using one chip.
| Original language | English |
|---|---|
| Title of host publication | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
| Pages | 94-95 |
| Number of pages | 2 |
| Publication status | Published - 2009 |
| Event | 2009 Symposium on VLSI Circuits - Kyoto, Japan Duration: 2009 Jun 16 → 2009 Jun 18 |
Other
| Other | 2009 Symposium on VLSI Circuits |
|---|---|
| Country | Japan |
| City | Kyoto |
| Period | 09/6/16 → 09/6/18 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
A scalable 3D processor by homogeneous chip stacking with inductive-coupling link. / Kohama, Yoshinori; Sugimori, Yasufumi; Saito, Shotaro; Hasegawa, Yohei; Sano, Toru; Kasuga, Kazutaka; Yoshida, Yoichi; Niitsu, Kiichi; Miura, Noriyuki; Amano, Hideharu; Kuroda, Tadahiro.
IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2009. p. 94-95 5205288.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A scalable 3D processor by homogeneous chip stacking with inductive-coupling link
AU - Kohama, Yoshinori
AU - Sugimori, Yasufumi
AU - Saito, Shotaro
AU - Hasegawa, Yohei
AU - Sano, Toru
AU - Kasuga, Kazutaka
AU - Yoshida, Yoichi
AU - Niitsu, Kiichi
AU - Miura, Noriyuki
AU - Amano, Hideharu
AU - Kuroda, Tadahiro
PY - 2009
Y1 - 2009
N2 - This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031mm2. Average execution time is reduced to 31% compared to that using one chip.
AB - This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031mm2. Average execution time is reduced to 31% compared to that using one chip.
UR - http://www.scopus.com/inward/record.url?scp=70449427842&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=70449427842&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:70449427842
SN - 9784863480018
SP - 94
EP - 95
BT - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
ER -