A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

Yoshinori Kohama, Yasufumi Sugimori, Shotaro Saito, Yohei Hasegawa, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Hideharu Amano, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031mm2. Average execution time is reduced to 31% compared to that using one chip.

Original languageEnglish
Title of host publication2009 Symposium on VLSI Circuits
Pages94-95
Number of pages2
Publication statusPublished - 2009 Nov 18
Event2009 Symposium on VLSI Circuits - Kyoto, Japan
Duration: 2009 Jun 162009 Jun 18

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2009 Symposium on VLSI Circuits
CountryJapan
CityKyoto
Period09/6/1609/6/18

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • Cite this

    Kohama, Y., Sugimori, Y., Saito, S., Hasegawa, Y., Sano, T., Kasuga, K., Yoshida, Y., Niitsu, K., Miura, N., Amano, H., & Kuroda, T. (2009). A scalable 3D processor by homogeneous chip stacking with inductive-coupling link. In 2009 Symposium on VLSI Circuits (pp. 94-95). [5205288] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).