A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

Yoshinori Kohama, Yasufumi Sugimori, Shotaro Saito, Yohei Hasegawa, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Hideharu Amano, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031mm2. Average execution time is reduced to 31% compared to that using one chip.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages94-95
Number of pages2
Publication statusPublished - 2009
Event2009 Symposium on VLSI Circuits - Kyoto, Japan
Duration: 2009 Jun 162009 Jun 18

Other

Other2009 Symposium on VLSI Circuits
CountryJapan
CityKyoto
Period09/6/1609/6/18

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Kohama, Y., Sugimori, Y., Saito, S., Hasegawa, Y., Sano, T., Kasuga, K., ... Kuroda, T. (2009). A scalable 3D processor by homogeneous chip stacking with inductive-coupling link. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 94-95). [5205288]

A scalable 3D processor by homogeneous chip stacking with inductive-coupling link. / Kohama, Yoshinori; Sugimori, Yasufumi; Saito, Shotaro; Hasegawa, Yohei; Sano, Toru; Kasuga, Kazutaka; Yoshida, Yoichi; Niitsu, Kiichi; Miura, Noriyuki; Amano, Hideharu; Kuroda, Tadahiro.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2009. p. 94-95 5205288.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kohama, Y, Sugimori, Y, Saito, S, Hasegawa, Y, Sano, T, Kasuga, K, Yoshida, Y, Niitsu, K, Miura, N, Amano, H & Kuroda, T 2009, A scalable 3D processor by homogeneous chip stacking with inductive-coupling link. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers., 5205288, pp. 94-95, 2009 Symposium on VLSI Circuits, Kyoto, Japan, 09/6/16.
Kohama Y, Sugimori Y, Saito S, Hasegawa Y, Sano T, Kasuga K et al. A scalable 3D processor by homogeneous chip stacking with inductive-coupling link. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2009. p. 94-95. 5205288
Kohama, Yoshinori ; Sugimori, Yasufumi ; Saito, Shotaro ; Hasegawa, Yohei ; Sano, Toru ; Kasuga, Kazutaka ; Yoshida, Yoichi ; Niitsu, Kiichi ; Miura, Noriyuki ; Amano, Hideharu ; Kuroda, Tadahiro. / A scalable 3D processor by homogeneous chip stacking with inductive-coupling link. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2009. pp. 94-95
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