A scheduling scheme for variable-length packets in an input-buffered ATM switch with priority of active buffer

In ATM (asynchronous transfer mode) we propose a VOQ (virtual output queuing) switch in which the same number of buffers as the number of output ports are provided in each input port, serving as an input-buffered switch to avoid HoL (head of line) blocking. In addition, in order to handle the recent increase of IP traffic, the IP-PIM (IP-parallel iterative matching) scheme is proposed as the scheduling scheme for the VOQ switch using variable-length packets. However, the IP-PIM scheme has the problem that the queue lengths in other buffers are increased, since cells belonging to the same packet are always handled continuously, which degrades the packet loss probability. Consequently, this paper proposes a scheduling scheme with active buffer priority in which the buffer receiving the cells belonging to the packet under consideration is defined as the active buffer and is given priority. In the proposed scheme, the queue length is reduced by giving the priority to the active buffer, and efficient switching is realized. The packet loss probability and the average packet delay are evaluated by computer simulation. It is found that the proposed scheme can greatly improve the packet loss probability compared to the conventional scheme, with degradation of the average packet delay by approximately 20 slots. It is also shown that a satisfactory loss probability is realized even if the buffer size is small, and that good expandability with regard to the switch size is achieved.