A series of modeling of plasma etching and damage reduction: Vertically integrated computer aided design for device processing

The present stage of a series of numerical modelings of the plasma etching processes is overviewed. Physical, chemical and electrical linkage among modules describing low-temperature plasma structure/function in a reactor, the profile and local charging evolution in a hole/ trench, and electrical device damage during etching will make it possible to prepare a technology computer aided design (TCAD) for the practical purpose of prediction and design of the etching process. This system will also help us to determine device arrangement and size in the system on a chip (SoC) in a closed integration system. Vertically integrated CAD for device processing (VicAddress) has been recently proposed by the authors. VicAddress will also provide a tool for discussing the etching processes between process engineers and device designers in the age of nanometer-scale device technology.