A study on snoop cache systems for single-chip multiprocessors

Takuya Terasawa, Keisuke Inoue, Hitoshi Kurosawa, Hideharu Amano

Research output: Contribution to journalArticle

Abstract

Progress in device design and implementation technologies will change the structure of bus-connected multiprocessors and allow them to be implemented on a single chip. In such an implementation, the speed of the bus inside the chip is far faster than that of the backplane bus, and data transfer between the chip and external devices will become a bottleneck. Many studies on snoop cache protocols have been made, but they generally assume that the cache memory is on a printed circuit board. In this paper, we first classify the snoop cache protocols in terms of accesses to off-chip shared memory, which will be the principal cause of performance degradation, and then compare them quantitatively. Evaluations are made with an instruction-level multiprocessor simulator and practical parallel applications, varying the cache size or the access latency of shared memory. The results show that an I/N/C protocol that actively uses the line transfers between caches achieves the highest performance under all conditions.

Original languageEnglish
Pages (from-to)62-72
Number of pages11
JournalSystems and Computers in Japan
Volume28
Issue number2
DOIs
Publication statusPublished - 1998 Feb

Keywords

  • Command-level simulator
  • Single-chip microprocessor
  • Snoop cache protocol

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Information Systems
  • Hardware and Architecture
  • Computational Theory and Mathematics

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