A System delay monitor exploiting automatic cell-based design flow and post-silicon calibration

Hayate Okuhara, Ryosuke Kazami, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this work, we present a low-overhead performance monitor which can emulate the maximum operational frequency of a target system by utilizing a delay chain so as to achieve efficient adaptive voltage control. The proposed monitor can be fully built by logic cells provided by general PDKs; thus, an automatic cell-based design flow can be used for its implementation. In addition, interconnect delay behaviors can also be imitated by exploiting wires which are automatically routed. In order to validate our concept, the proposed monitor is fabricated with a 65-nm Fully Depleted Silicon on Insulator (FD-SOI) technology. Real chip experiments reveal that the automated layout design can achieve the reasonable ability to delay emulation. Indeed, when the maximum operational frequency of a CNN accelerator is emulated, the proposed SDM achieved several percents of the performance tracking error. Also, its power overhead is only few percents.

Original languageEnglish
Title of host publicationProceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages32-37
Number of pages6
ISBN (Electronic)9781728148823
DOIs
Publication statusPublished - 2019 Oct
Event13th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019 - Singapore, Singapore
Duration: 2019 Oct 12019 Oct 4

Publication series

NameProceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019

Conference

Conference13th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019
CountrySingapore
CitySingapore
Period19/10/119/10/4

Fingerprint

Delay Systems
Silicon
Monitor
Calibration
Silicon on insulator technology
Percent
Cell
Voltage control
Particle accelerators
Silicon-on-insulator
Emulation
Wire
Interconnect
Accelerator
Layout
Chip
Voltage
Logic
Target
Experiments

Keywords

  • Adaptive voltage control
  • Low power design
  • Performance monitor
  • VLSI systems

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Control and Optimization

Cite this

Okuhara, H., Kazami, R., & Amano, H. (2019). A System delay monitor exploiting automatic cell-based design flow and post-silicon calibration. In Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019 (pp. 32-37). [8906740] (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MCSoC.2019.00012

A System delay monitor exploiting automatic cell-based design flow and post-silicon calibration. / Okuhara, Hayate; Kazami, Ryosuke; Amano, Hideharu.

Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 32-37 8906740 (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Okuhara, H, Kazami, R & Amano, H 2019, A System delay monitor exploiting automatic cell-based design flow and post-silicon calibration. in Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019., 8906740, Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019, Institute of Electrical and Electronics Engineers Inc., pp. 32-37, 13th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019, Singapore, Singapore, 19/10/1. https://doi.org/10.1109/MCSoC.2019.00012
Okuhara H, Kazami R, Amano H. A System delay monitor exploiting automatic cell-based design flow and post-silicon calibration. In Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 32-37. 8906740. (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019). https://doi.org/10.1109/MCSoC.2019.00012
Okuhara, Hayate ; Kazami, Ryosuke ; Amano, Hideharu. / A System delay monitor exploiting automatic cell-based design flow and post-silicon calibration. Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 32-37 (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).
@inproceedings{807f39ffbfd144c7912d660cdb9c1123,
title = "A System delay monitor exploiting automatic cell-based design flow and post-silicon calibration",
abstract = "In this work, we present a low-overhead performance monitor which can emulate the maximum operational frequency of a target system by utilizing a delay chain so as to achieve efficient adaptive voltage control. The proposed monitor can be fully built by logic cells provided by general PDKs; thus, an automatic cell-based design flow can be used for its implementation. In addition, interconnect delay behaviors can also be imitated by exploiting wires which are automatically routed. In order to validate our concept, the proposed monitor is fabricated with a 65-nm Fully Depleted Silicon on Insulator (FD-SOI) technology. Real chip experiments reveal that the automated layout design can achieve the reasonable ability to delay emulation. Indeed, when the maximum operational frequency of a CNN accelerator is emulated, the proposed SDM achieved several percents of the performance tracking error. Also, its power overhead is only few percents.",
keywords = "Adaptive voltage control, Low power design, Performance monitor, VLSI systems",
author = "Hayate Okuhara and Ryosuke Kazami and Hideharu Amano",
year = "2019",
month = "10",
doi = "10.1109/MCSoC.2019.00012",
language = "English",
series = "Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "32--37",
booktitle = "Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019",

}

TY - GEN

T1 - A System delay monitor exploiting automatic cell-based design flow and post-silicon calibration

AU - Okuhara, Hayate

AU - Kazami, Ryosuke

AU - Amano, Hideharu

PY - 2019/10

Y1 - 2019/10

N2 - In this work, we present a low-overhead performance monitor which can emulate the maximum operational frequency of a target system by utilizing a delay chain so as to achieve efficient adaptive voltage control. The proposed monitor can be fully built by logic cells provided by general PDKs; thus, an automatic cell-based design flow can be used for its implementation. In addition, interconnect delay behaviors can also be imitated by exploiting wires which are automatically routed. In order to validate our concept, the proposed monitor is fabricated with a 65-nm Fully Depleted Silicon on Insulator (FD-SOI) technology. Real chip experiments reveal that the automated layout design can achieve the reasonable ability to delay emulation. Indeed, when the maximum operational frequency of a CNN accelerator is emulated, the proposed SDM achieved several percents of the performance tracking error. Also, its power overhead is only few percents.

AB - In this work, we present a low-overhead performance monitor which can emulate the maximum operational frequency of a target system by utilizing a delay chain so as to achieve efficient adaptive voltage control. The proposed monitor can be fully built by logic cells provided by general PDKs; thus, an automatic cell-based design flow can be used for its implementation. In addition, interconnect delay behaviors can also be imitated by exploiting wires which are automatically routed. In order to validate our concept, the proposed monitor is fabricated with a 65-nm Fully Depleted Silicon on Insulator (FD-SOI) technology. Real chip experiments reveal that the automated layout design can achieve the reasonable ability to delay emulation. Indeed, when the maximum operational frequency of a CNN accelerator is emulated, the proposed SDM achieved several percents of the performance tracking error. Also, its power overhead is only few percents.

KW - Adaptive voltage control

KW - Low power design

KW - Performance monitor

KW - VLSI systems

UR - http://www.scopus.com/inward/record.url?scp=85076167396&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85076167396&partnerID=8YFLogxK

U2 - 10.1109/MCSoC.2019.00012

DO - 10.1109/MCSoC.2019.00012

M3 - Conference contribution

AN - SCOPUS:85076167396

T3 - Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019

SP - 32

EP - 37

BT - Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019

PB - Institute of Electrical and Electronics Engineers Inc.

ER -