A temporal correlation based port combination methodology for Networks-on-Chip on reconfigurable systems

Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize required hardware amount. Given the traffic characteristics of the target application and the expected hardware amount reduction rate, the algorithm automatically makes the port combination plan for the networks. Since the port combination technique has the advantage of almost keeping the topology, it does not affect the design of the other layers, such as task mapping and scheduling. The algorithm shows much better efficiency than the algorithm without temporal correlation. For the multimedia stream processing application, the algorithm can save 55% of the hardware amount without performance degradation, while the non-temporal correlation algorithm suffers from 30% performance loss.

Original languageEnglish
Title of host publicationProceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
Pages383-388
Number of pages6
DOIs
Publication statusPublished - 2007
Event2007 International Conference on Field Programmable Logic and Applications, FPL - Amsterdam, Netherlands
Duration: 2007 Aug 272007 Aug 29

Other

Other2007 International Conference on Field Programmable Logic and Applications, FPL
CountryNetherlands
CityAmsterdam
Period07/8/2707/8/29

Fingerprint

Hardware
Routers
Network-on-chip
Scheduling
Topology
Degradation
Processing

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Wang, D., Matsutani, H., Amano, H., & Koibuchi, M. (2007). A temporal correlation based port combination methodology for Networks-on-Chip on reconfigurable systems. In Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL (pp. 383-388). [4380676] https://doi.org/10.1109/FPL.2007.4380676

A temporal correlation based port combination methodology for Networks-on-Chip on reconfigurable systems. / Wang, Daihan; Matsutani, Hiroki; Amano, Hideharu; Koibuchi, Michihiro.

Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. 2007. p. 383-388 4380676.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wang, D, Matsutani, H, Amano, H & Koibuchi, M 2007, A temporal correlation based port combination methodology for Networks-on-Chip on reconfigurable systems. in Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL., 4380676, pp. 383-388, 2007 International Conference on Field Programmable Logic and Applications, FPL, Amsterdam, Netherlands, 07/8/27. https://doi.org/10.1109/FPL.2007.4380676
Wang D, Matsutani H, Amano H, Koibuchi M. A temporal correlation based port combination methodology for Networks-on-Chip on reconfigurable systems. In Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. 2007. p. 383-388. 4380676 https://doi.org/10.1109/FPL.2007.4380676
Wang, Daihan ; Matsutani, Hiroki ; Amano, Hideharu ; Koibuchi, Michihiro. / A temporal correlation based port combination methodology for Networks-on-Chip on reconfigurable systems. Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. 2007. pp. 383-388
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