TY - GEN
T1 - A variable-pipeline on-chip router optimized to traffic pattern
AU - Hirata, Yuto
AU - Matsutani, Hiroki
AU - Koibuchi, Michihiro
AU - Amano, Hideharu
PY - 2010
Y1 - 2010
N2 - Network-on-Chip (NoC) can be evaluated from various aspects, such as communication latency, throughput, and power consumption. The preference of these requirements depends on each application. An on-chip variable-pipeline (VP) router that can adapt to these requirements by dynamically reconfiguring its data path structure is proposed in this paper. In response to the communication pattern, it can change the pipeline structure, supply voltage, and operational frequency using the dynamic voltage and frequency scaling (DVFS). As the traffic load becomes high, the VP router uses a look-ahead two-cycle pipeline structure for exploiting the maximum frequency, while it behaves as a one-cycle router when a low latency is preferred. A three-cycle pipelined structure with an adaptive routing enables to dynamically avoid hotspots. Instead of a simple pipeline-stage unification which causes rapid decrease of the operating frequency, by speculatively executing multiple pipeline stages in parallel, the operating frequency gracefully decreases as the number of the pipeline stages increases. Simulation results show that the one-cycle mode offers the shortest communication latency, while the two-cycle mode achieves the highest throughput for SPLASH-2 benchmarks.
AB - Network-on-Chip (NoC) can be evaluated from various aspects, such as communication latency, throughput, and power consumption. The preference of these requirements depends on each application. An on-chip variable-pipeline (VP) router that can adapt to these requirements by dynamically reconfiguring its data path structure is proposed in this paper. In response to the communication pattern, it can change the pipeline structure, supply voltage, and operational frequency using the dynamic voltage and frequency scaling (DVFS). As the traffic load becomes high, the VP router uses a look-ahead two-cycle pipeline structure for exploiting the maximum frequency, while it behaves as a one-cycle router when a low latency is preferred. A three-cycle pipelined structure with an adaptive routing enables to dynamically avoid hotspots. Instead of a simple pipeline-stage unification which causes rapid decrease of the operating frequency, by speculatively executing multiple pipeline stages in parallel, the operating frequency gracefully decreases as the number of the pipeline stages increases. Simulation results show that the one-cycle mode offers the shortest communication latency, while the two-cycle mode achieves the highest throughput for SPLASH-2 benchmarks.
KW - interconnects
KW - network-on-chip
KW - router architecture
UR - http://www.scopus.com/inward/record.url?scp=79951639613&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79951639613&partnerID=8YFLogxK
U2 - 10.1145/1921249.1921263
DO - 10.1145/1921249.1921263
M3 - Conference contribution
AN - SCOPUS:79951639613
SN - 9781450303972
T3 - 3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43
SP - 57
EP - 62
BT - 3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43
T2 - 3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43
Y2 - 4 December 2010 through 4 December 2010
ER -