A variable-pipeline on-chip router optimized to traffic pattern

Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

Network-on-Chip (NoC) can be evaluated from various aspects, such as communication latency, throughput, and power consumption. The preference of these requirements depends on each application. An on-chip variable-pipeline (VP) router that can adapt to these requirements by dynamically reconfiguring its data path structure is proposed in this paper. In response to the communication pattern, it can change the pipeline structure, supply voltage, and operational frequency using the dynamic voltage and frequency scaling (DVFS). As the traffic load becomes high, the VP router uses a look-ahead two-cycle pipeline structure for exploiting the maximum frequency, while it behaves as a one-cycle router when a low latency is preferred. A three-cycle pipelined structure with an adaptive routing enables to dynamically avoid hotspots. Instead of a simple pipeline-stage unification which causes rapid decrease of the operating frequency, by speculatively executing multiple pipeline stages in parallel, the operating frequency gracefully decreases as the number of the pipeline stages increases. Simulation results show that the one-cycle mode offers the shortest communication latency, while the two-cycle mode achieves the highest throughput for SPLASH-2 benchmarks.

Original languageEnglish
Title of host publication3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43
Pages57-62
Number of pages6
DOIs
Publication statusPublished - 2010 Dec 1
Event3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43 - Atlanta, GA, United States
Duration: 2010 Dec 42010 Dec 4

Publication series

Name3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43

Other

Other3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43
CountryUnited States
CityAtlanta, GA
Period10/12/410/12/4

Keywords

  • interconnects
  • network-on-chip
  • router architecture

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A variable-pipeline on-chip router optimized to traffic pattern'. Together they form a unique fingerprint.

  • Cite this

    Hirata, Y., Matsutani, H., Koibuchi, M., & Amano, H. (2010). A variable-pipeline on-chip router optimized to traffic pattern. In 3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43 (pp. 57-62). (3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43). https://doi.org/10.1145/1921249.1921263