A VC-merge capable switch reducing buffer requirement by sharing reassembly buffers in MPLS

Kenji Sakamoto, Yoshiyuki Nishino, Iwao Sasase

Research output: Contribution to conferencePaperpeer-review

Abstract

In MPLS(MultiProtocol Label Switching), VC-merge(Virtual Circuit-merge) is known as a scalable technique to reduce the total number of VC. However, in the conventional VC-merge capable switch, the number of reassembly buffers greatly increases as switch size grows large. In this paper, we propose a VC-merge capable switch with less buffer requirement. In the proposed model, we can reduce the number of reassembly buffers and decrease the access speed of buffer memory since we can share reassembly buffers between the cells arrived at all input ports by controller. We compare the packet loss probability and the mean system delay performance of the proposed model with those of the conventional model by computer simulations. As a result, we show that the number of reassembly buffers decreases on the order of O(N) and the access speed of buffer memory becomes low. Therefore, the proposed model is effective in MPLS.

Original languageEnglish
Pages40-44
Number of pages5
Publication statusPublished - 2001 Dec 1
EventIEEE Global Telecommunicatins Conference GLOBECOM'01 - San Antonio, TX, United States
Duration: 2001 Nov 252001 Nov 29

Other

OtherIEEE Global Telecommunicatins Conference GLOBECOM'01
CountryUnited States
CitySan Antonio, TX
Period01/11/2501/11/29

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Global and Planetary Change

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