A versatile recognition processor for sensor network applications

Risako Takashima, Yuya Hanai, Yuichi Hori, Tadahiro Kuroda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    A versatile recognition processor is presented that comprises 2.1M transistors using a 90nm CMOS technology. It performs detection and recognition from image/video, sound and acceleration signals with energy consumption of sub-mJ/frame. The versatility and the power efficiency are attributed to optimal architecture design employing Haar-like Feature and Cascaded Classifier.

    Original languageEnglish
    Title of host publication2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
    Pages349-350
    Number of pages2
    DOIs
    Publication statusPublished - 2010 Apr 28
    Event2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei, Taiwan, Province of China
    Duration: 2010 Jan 182010 Jan 21

    Publication series

    NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

    Other

    Other2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
    CountryTaiwan, Province of China
    CityTaipei
    Period10/1/1810/1/21

    ASJC Scopus subject areas

    • Computer Science Applications
    • Computer Graphics and Computer-Aided Design
    • Electrical and Electronic Engineering

    Fingerprint Dive into the research topics of 'A versatile recognition processor for sensor network applications'. Together they form a unique fingerprint.

    Cite this