A versatile recognition processor for sensor network applications

Risako Takashima; Yuya Hanai; Yuichi Hori; Tadahiro Kuroda

doi:10.1109/ASPDAC.2010.5419867

A versatile recognition processor for sensor network applications

Risako Takashima, Yuya Hanai, Yuichi Hori, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A versatile recognition processor is presented that comprises 2.1M transistors using a 90nm CMOS technology. It performs detection and recognition from image/video, sound and acceleration signals with energy consumption of sub-mJ/frame. The versatility and the power efficiency are attributed to optimal architecture design employing Haar-like Feature and Cascaded Classifier.

Original language	English
Title of host publication	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Pages	349-350
Number of pages	2
DOIs	https://doi.org/10.1109/ASPDAC.2010.5419867
Publication status	Published - 2010 Apr 28
Event	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei, Taiwan, Province of China Duration: 2010 Jan 18 → 2010 Jan 21

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Country/Territory	Taiwan, Province of China
City	Taipei
Period	10/1/18 → 10/1/21

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ASPDAC.2010.5419867

Cite this

A versatile recognition processor for sensor network applications. / Takashima, Risako; Hanai, Yuya; Hori, Yuichi et al.

2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. 2010. p. 349-350 5419867 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Takashima, R, Hanai, Y, Hori, Y & Kuroda, T 2010, A versatile recognition processor for sensor network applications. in 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010., 5419867, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 349-350, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, Province of China, 10/1/18. https://doi.org/10.1109/ASPDAC.2010.5419867

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abstract = "A versatile recognition processor is presented that comprises 2.1M transistors using a 90nm CMOS technology. It performs detection and recognition from image/video, sound and acceleration signals with energy consumption of sub-mJ/frame. The versatility and the power efficiency are attributed to optimal architecture design employing Haar-like Feature and Cascaded Classifier.",

author = "Risako Takashima and Yuya Hanai and Yuichi Hori and Tadahiro Kuroda",

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A versatile recognition processor for sensor network applications

Abstract

Publication series

Other

ASJC Scopus subject areas

UN SDGs

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