TY - GEN
T1 - A vertical bubble flow network using inductive-coupling for 3-D CMPs
AU - Matsutani, Hiroki
AU - Take, Yasuhiro
AU - Sasaki, Daisuke
AU - Kimura, Masayuki
AU - Ono, Yuki
AU - Nishiyama, Yukinori
AU - Koibuchi, Michihiro
AU - Kuroda, Tadahiro
AU - Amano, Hideharu
N1 - Copyright:
Copyright 2011 Elsevier B.V., All rights reserved.
PY - 2011
Y1 - 2011
N2 - A wireless 3-D NoC architecture for CMPs, in which the number of processor and cache chips stacked in a package can be changed after the chip fabrication, is proposed by using the inductive coupling technology that can connect more than two known-good-dies without wire connections. Each chip has data transceivers for uplink and downlink in order to communicate with its neighboring chips in the package. These chips form a single vertical ring network so as to fully exploit the flexibility of the wireless approach that enables us to add, remove, and swap the chips in the ring. To avoid protocol and structural deadlocks in the ring network, we use the bubble flow control which is more flexible and efficient compared to the conventional VC-based deadlock avoidance. We implemented a real 3-D chip that has on-chip routers and inductive-coupling data transceivers using a 65nm process in order to show the feasibility of our proposal. The vertical bubble flow control is compared with the conventional VC-based approach and vertical bus in terms of the throughput, hardware amount, and application performance using a full system CMP simulator. The results show that the proposed vertical bubble flow network outperforms the VC-based approach by 7.9%-12.5% with a 33.5% smaller router area.
AB - A wireless 3-D NoC architecture for CMPs, in which the number of processor and cache chips stacked in a package can be changed after the chip fabrication, is proposed by using the inductive coupling technology that can connect more than two known-good-dies without wire connections. Each chip has data transceivers for uplink and downlink in order to communicate with its neighboring chips in the package. These chips form a single vertical ring network so as to fully exploit the flexibility of the wireless approach that enables us to add, remove, and swap the chips in the ring. To avoid protocol and structural deadlocks in the ring network, we use the bubble flow control which is more flexible and efficient compared to the conventional VC-based deadlock avoidance. We implemented a real 3-D chip that has on-chip routers and inductive-coupling data transceivers using a 65nm process in order to show the feasibility of our proposal. The vertical bubble flow control is compared with the conventional VC-based approach and vertical bus in terms of the throughput, hardware amount, and application performance using a full system CMP simulator. The results show that the proposed vertical bubble flow network outperforms the VC-based approach by 7.9%-12.5% with a 33.5% smaller router area.
KW - 3-D ICs
KW - inductive-coupling
KW - many-core
KW - on-chip networks
UR - http://www.scopus.com/inward/record.url?scp=79960319724&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79960319724&partnerID=8YFLogxK
U2 - 10.1145/1999946.1999955
DO - 10.1145/1999946.1999955
M3 - Conference contribution
AN - SCOPUS:79960319724
SN - 9781450307208
T3 - NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip
SP - 49
EP - 56
BT - NOCS 2011
T2 - 5th ACM/IEEE International Symposium on Networks-on-Chip, NOCS 2011
Y2 - 1 May 2011 through 4 May 2011
ER -