A very-high-speed ATM switch architecture using internal speed-up technique

Kouichi Genda, Yukihiro Doi, Ken Ichi Endo, Naoaki Yamanaka

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

An internal speed-up crossbar-type ATM switch architecture is proposed. This switch accommodates 10 Gbit/s cell streams from AHMs in order to guarantee the QoS of switched cells. A new high-speed arbitration algorithm using three buses on each output line, called the bi-directional arbiter, is used. It handles output contention about twice as fast as the conventional ring-arbiter and has the same fairness function. It increases the switch throughput to 160 Gbit/s efficiently. By combining the high-speed switch and AHMs, it will be able to make a sub-terabit/s ATM switching system for future Broadband ISDN networks.

Original languageEnglish
Pages (from-to)20-27
Number of pages8
JournalNTT Review
Volume9
Issue number2
Publication statusPublished - 1997 Mar
Externally publishedYes

Fingerprint

Automatic teller machines
Switches
Switching systems
Quality of service
Throughput

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Networks and Communications

Cite this

A very-high-speed ATM switch architecture using internal speed-up technique. / Genda, Kouichi; Doi, Yukihiro; Endo, Ken Ichi; Yamanaka, Naoaki.

In: NTT Review, Vol. 9, No. 2, 03.1997, p. 20-27.

Research output: Contribution to journalArticle

Genda, Kouichi ; Doi, Yukihiro ; Endo, Ken Ichi ; Yamanaka, Naoaki. / A very-high-speed ATM switch architecture using internal speed-up technique. In: NTT Review. 1997 ; Vol. 9, No. 2. pp. 20-27.
@article{645102af0065421d89426da5fcfdfe5d,
title = "A very-high-speed ATM switch architecture using internal speed-up technique",
abstract = "An internal speed-up crossbar-type ATM switch architecture is proposed. This switch accommodates 10 Gbit/s cell streams from AHMs in order to guarantee the QoS of switched cells. A new high-speed arbitration algorithm using three buses on each output line, called the bi-directional arbiter, is used. It handles output contention about twice as fast as the conventional ring-arbiter and has the same fairness function. It increases the switch throughput to 160 Gbit/s efficiently. By combining the high-speed switch and AHMs, it will be able to make a sub-terabit/s ATM switching system for future Broadband ISDN networks.",
author = "Kouichi Genda and Yukihiro Doi and Endo, {Ken Ichi} and Naoaki Yamanaka",
year = "1997",
month = "3",
language = "English",
volume = "9",
pages = "20--27",
journal = "NTT Review",
issn = "0915-2334",
publisher = "Telecommunications Association",
number = "2",

}

TY - JOUR

T1 - A very-high-speed ATM switch architecture using internal speed-up technique

AU - Genda, Kouichi

AU - Doi, Yukihiro

AU - Endo, Ken Ichi

AU - Yamanaka, Naoaki

PY - 1997/3

Y1 - 1997/3

N2 - An internal speed-up crossbar-type ATM switch architecture is proposed. This switch accommodates 10 Gbit/s cell streams from AHMs in order to guarantee the QoS of switched cells. A new high-speed arbitration algorithm using three buses on each output line, called the bi-directional arbiter, is used. It handles output contention about twice as fast as the conventional ring-arbiter and has the same fairness function. It increases the switch throughput to 160 Gbit/s efficiently. By combining the high-speed switch and AHMs, it will be able to make a sub-terabit/s ATM switching system for future Broadband ISDN networks.

AB - An internal speed-up crossbar-type ATM switch architecture is proposed. This switch accommodates 10 Gbit/s cell streams from AHMs in order to guarantee the QoS of switched cells. A new high-speed arbitration algorithm using three buses on each output line, called the bi-directional arbiter, is used. It handles output contention about twice as fast as the conventional ring-arbiter and has the same fairness function. It increases the switch throughput to 160 Gbit/s efficiently. By combining the high-speed switch and AHMs, it will be able to make a sub-terabit/s ATM switching system for future Broadband ISDN networks.

UR - http://www.scopus.com/inward/record.url?scp=0342268818&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0342268818&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0342268818

VL - 9

SP - 20

EP - 27

JO - NTT Review

JF - NTT Review

SN - 0915-2334

IS - 2

ER -