Abstract
Hall thruster is a sort of electric propulsion and has been studied in many research institutes. In the design process of Hall thruster, a numerical simulation called Full-PIC (Particle-In-Cell) method is used. Although this simulation provides high accurate result, it is known as a very time consuming job. In this paper, we present a study of acceleration of Full-PIC simulation on a CPU-FPGA tightly coupled environment. A high-load part is selected and off-loaded to an FPGA. Zynq-7000 and Vivado HLS are used for implementation. To optimize the implemented design, every target process was divided into some parts for pipelining and adjustment interval. Three off-loaded subroutines named "field-source", "particle-att-ion" and "particle-att-ele" achieved 8.53 times, 12.78 times and 14.95 times performance compared with the software execution, respectively. The total execution time of target part is sped up 5.17 times compared with Cortex-A9 667MHz in Zynq.
Original language | English |
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Title of host publication | Proceedings - IEEE 10th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 8-14 |
Number of pages | 7 |
ISBN (Electronic) | 9781509035304 |
DOIs | |
Publication status | Published - 2016 Dec 5 |
Event | 10th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016 - Lyon, France Duration: 2016 Sep 21 → 2016 Sep 23 |
Other
Other | 10th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016 |
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Country/Territory | France |
City | Lyon |
Period | 16/9/21 → 16/9/23 |
Keywords
- FPGA
- hall thruster
- plasma simulation
- Zynq
ASJC Scopus subject areas
- Computer Networks and Communications
- Hardware and Architecture