TY - GEN
T1 - Accelerator-in-switch
T2 - 27th International Conference on Field Programmable Logic and Applications, FPL 2017
AU - Tsuruta, Chiharu
AU - Kaneda, Takahiro
AU - Nishikawa, Naoki
AU - Amano, Hideharu
N1 - Funding Information:
The present study was supported in part by the JST/CREST program entitled ”Research and Development on Unified Environment of Accelerated Computing and Interconnection for Post-Petascale Era” in the research area of ”Development of System Software Technologies for post-Peta Scale High Performance Computing”.
Publisher Copyright:
© 2017 Ghent University.
PY - 2017/10/2
Y1 - 2017/10/2
N2 - Accelerator-in-Switch (AiS) is a framework for building an accelerator logic tightly coupled with a switching hub in a single FPGA for high performance computation with heterogeneous environment with CPUs and GPUs. AiS is implemented on a partial reconfigurable region of an FPGA whose permanent region is used for a switching hub. A port of the switching hub is connected to the registers and local memory of AiS directly. AiS has a standard interface for a standard bus (Avalon MM bus, here) to exchange data between on-board DDR SDRAM and the local memory, and various types of accelerators can be implemented just by providing such an interface. The data input and output are performed with the DMA controller inside the switching hub with the shared memory model between host CPUs and GPUs. We implemented two example accelerators: a reduction calculator for a radiation transfer equations solver (RED) and LET generator for N-body simulation (LET) were implemented as the AiS on PEACH3, a switching hub for a PCIe direct interconnection network with Altera's Stratix V. The use of partial reconfiguration makes it possible to switch multiple accelerators without stopping the switching hub. As a result, we reduced the time for place&route of an accelerator by 47% compared to the case of the design combining the accelerator into the switching hub.
AB - Accelerator-in-Switch (AiS) is a framework for building an accelerator logic tightly coupled with a switching hub in a single FPGA for high performance computation with heterogeneous environment with CPUs and GPUs. AiS is implemented on a partial reconfigurable region of an FPGA whose permanent region is used for a switching hub. A port of the switching hub is connected to the registers and local memory of AiS directly. AiS has a standard interface for a standard bus (Avalon MM bus, here) to exchange data between on-board DDR SDRAM and the local memory, and various types of accelerators can be implemented just by providing such an interface. The data input and output are performed with the DMA controller inside the switching hub with the shared memory model between host CPUs and GPUs. We implemented two example accelerators: a reduction calculator for a radiation transfer equations solver (RED) and LET generator for N-body simulation (LET) were implemented as the AiS on PEACH3, a switching hub for a PCIe direct interconnection network with Altera's Stratix V. The use of partial reconfiguration makes it possible to switch multiple accelerators without stopping the switching hub. As a result, we reduced the time for place&route of an accelerator by 47% compared to the case of the design combining the accelerator into the switching hub.
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U2 - 10.23919/FPL.2017.8056846
DO - 10.23919/FPL.2017.8056846
M3 - Conference contribution
AN - SCOPUS:85034440849
T3 - 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017
BT - 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017
A2 - Gohringer, Diana
A2 - Stroobandt, Dirk
A2 - Mentens, Nele
A2 - Santambrogio, Marco
A2 - Nurmi, Jari
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 4 September 2017 through 6 September 2017
ER -