Over the past decade, the power consumption has been one of the main design challenges in Network-on-Chips (NoCs) as it significantly defines the performance of a given Chip-Multiprocessor (CMP). Body bias control is one of the solutions that provide an efficient trade-off between leakage power and performance. However, employing such a method is not straightforward since several factors should be taken into consideration, especially when adaptively implemented on-chip. In this paper, we propose a new router design and on-chip body bias control mechanism to adaptively control the body bias voltages supply in ultra low-power NoC systems. With the help of a light-weight monitoring circuit, the proposed router predicts the traffic load at each input-port and accordingly adjusts its pipeline depth in a fine-grained fashion. To satisfy the timing constraints, the router adaptively supplies each one of its input-ports with the appropriate body bias voltages to either boost the performance or to reduce the leakage power at the standby state. The evaluation results, using the SOTB 65nm Fully Depleted Silicon On Insulator (FD-SOI) technology, shows the ability of the proposed router in reducing both dynamic and static energies. When compared to two fixed-pipeline baseline routers (3-stages and 2-stages), the total energy reduction could reach up to 67% and 59%, respectively. At the same time, a reasonable performance tendency can be obtained with less than 6% area overhead.