Adding slow-silent virtual channels for low-power on-chip networks

Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

Abstract

In this paper, we introduce the use of slow-silent virtual channels to reduce the switching power of on-chip networks while keeping the leakage power small. Adding virtual channels to a network improves the throughput until each link bandwidth is saturated. This enables us to reduce the switching power of on-chip networks by decreasing their operating frequency and supply voltage. However, adding virtual channels increases the leakage power of routers as well as the area due to their large buffers; so the runtime power gating is applied to individual virtual channels to eliminate this problem. We evaluate the performance of slow-silent virtual channels by using real application traces, and their power consumption (switching and leakage) is evaluated based on the detailed design of a virtual-channel router placed and routed with a 90nm technology. These evaluation results show that a network with three or four virtual channels achieves the best energy efficiency in a uniform traffic. In the cases of neighboring communications, a network with two virtual channels is better than the other networks with more virtual channels, because the performance improvement from no virtual channel to two virtual channels is the largest and their frequency and supply voltage can also be reduced well in these cases.

Original languageEnglish
Title of host publicationProceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008
Pages23-32
Number of pages10
DOIs
Publication statusPublished - 2008
Event2nd IEEE International Symposium on Networks-on-Chip, NOCS 2008 - Newcastle upon Tyne, United Kingdom
Duration: 2008 Apr 72008 Apr 11

Other

Other2nd IEEE International Symposium on Networks-on-Chip, NOCS 2008
CountryUnited Kingdom
CityNewcastle upon Tyne
Period08/4/708/4/11

Fingerprint

Routers
Electric potential
Telecommunication links
Energy efficiency
Electric power utilization
Throughput
Bandwidth
Communication
Network-on-chip

ASJC Scopus subject areas

  • Computer Science(all)

Cite this

Matsutani, H., Koibuchi, M., Wang, D., & Amano, H. (2008). Adding slow-silent virtual channels for low-power on-chip networks. In Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008 (pp. 23-32). [4492722] https://doi.org/10.1109/NOCS.2008.4492722

Adding slow-silent virtual channels for low-power on-chip networks. / Matsutani, Hiroki; Koibuchi, Michihiro; Wang, Daihan; Amano, Hideharu.

Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. 2008. p. 23-32 4492722.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Matsutani, H, Koibuchi, M, Wang, D & Amano, H 2008, Adding slow-silent virtual channels for low-power on-chip networks. in Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008., 4492722, pp. 23-32, 2nd IEEE International Symposium on Networks-on-Chip, NOCS 2008, Newcastle upon Tyne, United Kingdom, 08/4/7. https://doi.org/10.1109/NOCS.2008.4492722
Matsutani H, Koibuchi M, Wang D, Amano H. Adding slow-silent virtual channels for low-power on-chip networks. In Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. 2008. p. 23-32. 4492722 https://doi.org/10.1109/NOCS.2008.4492722
Matsutani, Hiroki ; Koibuchi, Michihiro ; Wang, Daihan ; Amano, Hideharu. / Adding slow-silent virtual channels for low-power on-chip networks. Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. 2008. pp. 23-32
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