Since the end of Dennard scaling is almost approaching, new types of computing methods and architectures are being sought. As one of such architectures, hardware solvers for satisfiability (SAT) problems are getting more attentions these days because combinatorial optimization problems residing in many types of Internet-of-Things (IoT) and embedded systems applications can be transformed to SAT problems. In this paper, we present a novel, fast FPGA-based SAT solver with fine-grained parallelism. We particularly focus on a recently-developed SAT algorithm, AmoebaSAT, which abstracts shape-changing dynamics of an amoeba. Our hardware AmoebaSAT solver can enjoy high parallelism in quickly searching a solution (i.e., a satisfiable combination of variables assignment) for a given SAT instance, with a help of stochastic features to avoid local search. Our evaluations demonstrated that our work can outperform state-of-the-art on WalkSAT, another SAT algorithm which has been popular and widely-used for decades.