An 0.5V, 0.91pJ/bit, 1.1Gb/s/ch transceiver in 65nm CMOS for high-speed wireless proximity interface

Takeshi Matsubara, Isamu Hayashi, Abul Hasan Johari, Satoshi Kumaki, Kaoru Kohira, Tadahiro Kuroda, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper presents a pulse-based inductivecoupling transceiver in 65nm CMOS for high-speed wireless proximity communication. The transceiver operates at 0.5V supply voltage. A pulse bootstrap circuit and a common drain output stage enables transmitter to operate at ultralow voltage. In the receiver, a gain boosted common-gate amplifier is used to reduce the input impedance and suppress the ringing of received pulse signal. The data rate and energy efficiency are 1.1Gb/s/ch and 0.91pJ/bit, respectively at 0.5V supply voltage. The data rate can be increased to 1.7Gb/s/ch at 0.75V.

Original languageEnglish
Title of host publication2011 IEEE Radio and Wireless Week, RWW 2011 - 2011 IEEE Radio and Wireless Symposium, RWS 2011
Pages74-77
Number of pages4
DOIs
Publication statusPublished - 2011
Event2011 IEEE Radio and Wireless Symposium, RWS 2011 - Phoenix, AZ, United States
Duration: 2011 Jan 162011 Jan 19

Other

Other2011 IEEE Radio and Wireless Symposium, RWS 2011
CountryUnited States
CityPhoenix, AZ
Period11/1/1611/1/19

Fingerprint

Transceivers
supply
Electric potential
Pulse circuits
recipient
energy
efficiency
Energy efficiency
communication
Transmitters
Communication

Keywords

  • Bootstrap
  • High speed interface
  • Inductive-coupling
  • Proximity communication
  • Ultra-low voltage

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Communication

Cite this

Matsubara, T., Hayashi, I., Johari, A. H., Kumaki, S., Kohira, K., Kuroda, T., & Ishikuro, H. (2011). An 0.5V, 0.91pJ/bit, 1.1Gb/s/ch transceiver in 65nm CMOS for high-speed wireless proximity interface. In 2011 IEEE Radio and Wireless Week, RWW 2011 - 2011 IEEE Radio and Wireless Symposium, RWS 2011 (pp. 74-77). [5725473] https://doi.org/10.1109/RWS.2011.5725473

An 0.5V, 0.91pJ/bit, 1.1Gb/s/ch transceiver in 65nm CMOS for high-speed wireless proximity interface. / Matsubara, Takeshi; Hayashi, Isamu; Johari, Abul Hasan; Kumaki, Satoshi; Kohira, Kaoru; Kuroda, Tadahiro; Ishikuro, Hiroki.

2011 IEEE Radio and Wireless Week, RWW 2011 - 2011 IEEE Radio and Wireless Symposium, RWS 2011. 2011. p. 74-77 5725473.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Matsubara, T, Hayashi, I, Johari, AH, Kumaki, S, Kohira, K, Kuroda, T & Ishikuro, H 2011, An 0.5V, 0.91pJ/bit, 1.1Gb/s/ch transceiver in 65nm CMOS for high-speed wireless proximity interface. in 2011 IEEE Radio and Wireless Week, RWW 2011 - 2011 IEEE Radio and Wireless Symposium, RWS 2011., 5725473, pp. 74-77, 2011 IEEE Radio and Wireless Symposium, RWS 2011, Phoenix, AZ, United States, 11/1/16. https://doi.org/10.1109/RWS.2011.5725473
Matsubara T, Hayashi I, Johari AH, Kumaki S, Kohira K, Kuroda T et al. An 0.5V, 0.91pJ/bit, 1.1Gb/s/ch transceiver in 65nm CMOS for high-speed wireless proximity interface. In 2011 IEEE Radio and Wireless Week, RWW 2011 - 2011 IEEE Radio and Wireless Symposium, RWS 2011. 2011. p. 74-77. 5725473 https://doi.org/10.1109/RWS.2011.5725473
Matsubara, Takeshi ; Hayashi, Isamu ; Johari, Abul Hasan ; Kumaki, Satoshi ; Kohira, Kaoru ; Kuroda, Tadahiro ; Ishikuro, Hiroki. / An 0.5V, 0.91pJ/bit, 1.1Gb/s/ch transceiver in 65nm CMOS for high-speed wireless proximity interface. 2011 IEEE Radio and Wireless Week, RWW 2011 - 2011 IEEE Radio and Wireless Symposium, RWS 2011. 2011. pp. 74-77
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