An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept

Peter Toth, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a wide-dynamic-range high-resolution timedomain converter concept tailored for low-power sensor interfaces. The unique system structure applies different techniques to reduce circuit complexity, power consumption, and noise sensitivity. A multi-cycle concept allows a virtual delay line extension and is applied to achieve high resolution down to 1ns. At the same time, it expands the dynamic range drastically up to 2.35 ms. Moreover, individually tunable delay elements in the range of 1ns to 12 ns allow on-demand flexible operation in a low- or high-resolution mode for smart sensing applications and flexible power control. The concept of this paper is evaluated by a custom-designed FPGA supported PCB. The presented concept is highly suitable for onchip integration.

Original languageEnglish
Title of host publicationProceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages105-106
Number of pages2
ISBN (Electronic)9781450379991
DOIs
Publication statusPublished - 2021 Jan 18
Event26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021 - Virtual, Online, Japan
Duration: 2021 Jan 182021 Jan 21

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
Country/TerritoryJapan
CityVirtual, Online
Period21/1/1821/1/21

Keywords

  • Low-Power TDC
  • Multi-Stage TDC
  • Sensor Interface
  • Time-Domain Converter (TDC)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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