An 8 bit 0.3-0.8 v 0.2-40 MS/s 2-bit/Step SAR ADC with successively activated threshold configuring comparators in 40 nm CMOS

Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

A 0.3-0.8 V low-power 2-bit/step asynchronous successive approximation register analog-to-digital converter (ADC) is presented. A low-power 2-bit/step operation technique is proposed which uses dynamic threshold configuring comparator instead of multiple digital-to-analog converters (DACs). Power and area overhead is minimized by successively activated comparators. The comparator threshold is configured by simple Vcm biased current source, which keep the ADC free from power supply variations over 10%. Simple digital calibration is enabled by generating the reference internally. The prototype ADC fabricated in a 40 nm CMOS achieved a 44.3 dB signal-to-noise-plus-distortion ratio (SNDR) with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 4.8 fJ/conv-step at 0.4 V and operates down to 0.3 V.

Original languageEnglish
Article number6748934
Pages (from-to)356-368
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume23
Issue number2
DOIs
Publication statusPublished - 2015 Feb 1

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Digital to analog conversion
Calibration
Electric potential

Keywords

  • 2-bit/step
  • extremely low voltage
  • low power
  • SAR ADC
  • threshold configuring comparator.

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

An 8 bit 0.3-0.8 v 0.2-40 MS/s 2-bit/Step SAR ADC with successively activated threshold configuring comparators in 40 nm CMOS. / Yoshioka, Kentaro; Shikata, Akira; Sekimoto, Ryota; Kuroda, Tadahiro; Ishikuro, Hiroki.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 2, 6748934, 01.02.2015, p. 356-368.

Research output: Contribution to journalArticle

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