Abstract
An extremely low power and area efficient threshold configuring ADC (TC-ADC) for time interleaved ADC is proposed. The threshold configuring comparator (TCC) performs a binary search. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm 2 and when calibration circuit included, 0.0058 mm2. With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC |
| Pages | 31-32 |
| Number of pages | 2 |
| DOIs | |
| Publication status | Published - 2014 |
| Event | 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Suntec, Singapore Duration: 2014 Jan 20 → 2014 Jan 23 |
Other
| Other | 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 |
|---|---|
| Country | Singapore |
| City | Suntec |
| Period | 14/1/20 → 14/1/23 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Computer Science Applications
- Computer Graphics and Computer-Aided Design
Cite this
An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. / Yoshioka, Kentaro; Shikata, Akira; Sekimoto, Ryota; Kuroda, Tadahiro; Ishikuro, Hiroki.
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2014. p. 31-32 6742859.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique
AU - Yoshioka, Kentaro
AU - Shikata, Akira
AU - Sekimoto, Ryota
AU - Kuroda, Tadahiro
AU - Ishikuro, Hiroki
PY - 2014
Y1 - 2014
N2 - An extremely low power and area efficient threshold configuring ADC (TC-ADC) for time interleaved ADC is proposed. The threshold configuring comparator (TCC) performs a binary search. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm 2 and when calibration circuit included, 0.0058 mm2. With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC.
AB - An extremely low power and area efficient threshold configuring ADC (TC-ADC) for time interleaved ADC is proposed. The threshold configuring comparator (TCC) performs a binary search. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm 2 and when calibration circuit included, 0.0058 mm2. With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC.
UR - http://www.scopus.com/inward/record.url?scp=84897869081&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84897869081&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2014.6742859
DO - 10.1109/ASPDAC.2014.6742859
M3 - Conference contribution
AN - SCOPUS:84897869081
SN - 9781479928163
SP - 31
EP - 32
BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
ER -