An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique

Kentaro Yoshioka; Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro

doi:10.1109/ASPDAC.2014.6742859

An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique

Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

Department of Electronics and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

An extremely low power and area efficient threshold configuring ADC (TC-ADC) for time interleaved ADC is proposed. The threshold configuring comparator (TCC) performs a binary search. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm ² and when calibration circuit included, 0.0058 mm². With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC.

Original language	English
Title of host publication	2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings
Pages	31-32
Number of pages	2
DOIs	https://doi.org/10.1109/ASPDAC.2014.6742859
Publication status	Published - 2014 Mar 27
Event	2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Suntec, Singapore Duration: 2014 Jan 20 → 2014 Jan 23

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other	2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014
Country/Territory	Singapore
City	Suntec
Period	14/1/20 → 14/1/23

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2014.6742859

Cite this

Yoshioka, K., Shikata, A., Sekimoto, R., Kuroda, T., & Ishikuro, H. (2014). An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. In 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings (pp. 31-32). [6742859] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2014.6742859

An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. / Yoshioka, Kentaro; Shikata, Akira; Sekimoto, Ryota et al.

2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings. 2014. p. 31-32 6742859 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yoshioka, K, Shikata, A, Sekimoto, R, Kuroda, T & Ishikuro, H 2014, An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. in 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings., 6742859, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 31-32, 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014, Suntec, Singapore, 14/1/20. https://doi.org/10.1109/ASPDAC.2014.6742859

Yoshioka K, Shikata A, Sekimoto R, Kuroda T, Ishikuro H. An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. In 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings. 2014. p. 31-32. 6742859. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1109/ASPDAC.2014.6742859

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An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique

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