An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique

Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

An extremely low power and area efficient threshold configuring ADC (TC-ADC) for time interleaved ADC is proposed. The threshold configuring comparator (TCC) performs a binary search. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm 2 and when calibration circuit included, 0.0058 mm2. With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages31-32
Number of pages2
DOIs
Publication statusPublished - 2014
Event2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Suntec, Singapore
Duration: 2014 Jan 202014 Jan 23

Other

Other2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014
CountrySingapore
CitySuntec
Period14/1/2014/1/23

Fingerprint

Electric potential
Interpolation
Calibration
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Yoshioka, K., Shikata, A., Sekimoto, R., Kuroda, T., & Ishikuro, H. (2014). An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 31-32). [6742859] https://doi.org/10.1109/ASPDAC.2014.6742859

An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. / Yoshioka, Kentaro; Shikata, Akira; Sekimoto, Ryota; Kuroda, Tadahiro; Ishikuro, Hiroki.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2014. p. 31-32 6742859.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yoshioka, K, Shikata, A, Sekimoto, R, Kuroda, T & Ishikuro, H 2014, An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC., 6742859, pp. 31-32, 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014, Suntec, Singapore, 14/1/20. https://doi.org/10.1109/ASPDAC.2014.6742859
Yoshioka K, Shikata A, Sekimoto R, Kuroda T, Ishikuro H. An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2014. p. 31-32. 6742859 https://doi.org/10.1109/ASPDAC.2014.6742859
Yoshioka, Kentaro ; Shikata, Akira ; Sekimoto, Ryota ; Kuroda, Tadahiro ; Ishikuro, Hiroki. / An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2014. pp. 31-32
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