An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator

Kentaro Yoshioka; Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro

doi:10.1109/ESSCIRC.2012.6341365

An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator

Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

Department of Electronics and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

17 Citations (Scopus)

Abstract

An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple V_cm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V.

Original language	English
Title of host publication	2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012
Pages	381-384
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIRC.2012.6341365
Publication status	Published - 2012 Dec 14
Event	38th European Solid State Circuits Conference, ESSCIRC 2012 - Bordeaux, France Duration: 2012 Sept 17 → 2012 Sept 21

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Other

Other	38th European Solid State Circuits Conference, ESSCIRC 2012
Country/Territory	France
City	Bordeaux
Period	12/9/17 → 12/9/21

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ESSCIRC.2012.6341365

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An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator. / Yoshioka, Kentaro; Shikata, Akira; Sekimoto, Ryota et al.
2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012. 2012. p. 381-384 6341365 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yoshioka, K, Shikata, A, Sekimoto, R, Kuroda, T & Ishikuro, H 2012, An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator. in 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012., 6341365, European Solid-State Circuits Conference, pp. 381-384, 38th European Solid State Circuits Conference, ESSCIRC 2012, Bordeaux, France, 12/9/17. https://doi.org/10.1109/ESSCIRC.2012.6341365

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abstract = "An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V.",

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AB - An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V.

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An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator

Abstract

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